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Re: [PATCH, FT32] gdb and sim support

On 23 Mar 2015 19:20, James Bowman wrote:
> +/*
> + * FT32 is a Harvard architecture: RAM and code occupy
> + * different address spaces.
> + *
> + * sim and gdb model FT32 memory by adding 0x800000 to RAM
> + * addresses. This means that sim/gdb can treat all addresses
> + * similarly.
> + * 
> + * The address space looks like:
> + *
> + *    00000   start of code memory
> + *    3ffff   end of code memory
> + *   800000   start of RAM
> + *   80ffff   end of RAM
> + */

do they actually occupy different address spaces ?  that is to say, if you put 
address 0 into a register and try to do a data load/store, does it throw an 
exception ?  or is it transparently routed to 800000 ?

Blackfin cpus are described as Harvard because it has on-chip memory that can 
only be accessed either as insn or as data, but it's a unified memory map.  for 
example, if you were to execute (jump to) 0xffa00000, it'd work, but if you 
tried to do a load/store with 0xffa00000, the hardware would throw an exception.  
if you were to execute (jump to) 0xff800000, the hardware would throw an 
exception, but you could do a load/store just fine.

i'm not sure gdb or the sim generally support processors with overlapping 
memory.  i.e. a $pc of 0 is completely different from a $r0 (data register) with 
the address of 0.

i tried to grab some datasheets from, but (1) couldn't seem to find 
anything on the architecture (just datasheets for specific parts which covered 
more system devices than the ISA/core) and (2) it's crazy slow to download from.

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