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[PATCH] sim: bfin: handle large shift values with accumulator shift insns
- From: Mike Frysinger <vapier at gentoo dot org>
- To: gdb-patches at sourceware dot org
- Cc: Robin Getz <robin dot getz at analog dot com>
- Date: Sat, 18 Jun 2011 16:59:38 -0400
- Subject: [PATCH] sim: bfin: handle large shift values with accumulator shift insns
From: Robin Getz <robin.getz@analog.com>
When the shift magnitude exceeds 32 bits, the values rotate around (since
the hardware is actually a barrel shifter). So handle this edge case,
update the corresponding AV bit in ASTAT which was missing previously,
and tweak the AZ setting based on how the hardware behaves.
Committed.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-21 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32shiftimm_0): When shift is greater than
32, perform a left shift. Update the corresponding AV bit. Set
AZ when the low 32bits are also zero.
---
sim/bfin/bfin-sim.c | 10 ++++++++--
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 11eea3a..b982aaf 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -5775,11 +5775,17 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (sop == 0)
acc <<= shiftup;
else
- acc >>= shiftdn;
+ {
+ if (shiftdn <= 32)
+ acc >>= shiftdn;
+ else
+ acc <<= 32 - (shiftdn & 0x1f);
+ }
SET_AREG (HLs, acc);
+ SET_ASTATREG (av[HLs], 0);
SET_ASTATREG (an, !!(acc & 0x8000000000ull));
- SET_ASTATREG (az, acc == 0);
+ SET_ASTATREG (az, (acc & 0xFFFFFFFFFF) == 0);
}
else if (sop == 1 && sopcde == 1 && bit8 == 0)
{
--
1.7.5.3