This is the mail archive of the gdb-patches@sourceware.org mailing list for the GDB project.
Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]
[PATCH] sim: bfin: move model data into machs.h

From: Mike Frysinger <vapier at gentoo dot org>
To: gdb-patches at sourceware dot org
Cc: toolchain-devel at blackfin dot uclinux dot org
Date: Wed, 25 May 2011 08:54:34 -0400
Subject: [PATCH] sim: bfin: move model data into machs.h
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header.  The models themselves don't care about
where they're mapped, only the mach code does.  This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding.  Such as when a newer device model is
created, but with incompatible register names/layouts.

Committed.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2011-05-25  Mike Frysinger  <vapier@gentoo.org>

	* dv-bfin_cec.h (BFIN_COREMMR_CEC_{BASE,SIZE}): Move to ...
	* dv-bfin_ctimer.h (BFIN_COREMMR_CTIMER_{BASE,SIZE}): Move to ...
	* dv-bfin_dma.h (BFIN_MMR_DMA_SIZE): Move to ...
	* dv-bfin_dmac.h (BFIN_MMR_DMAC{0,1}_BASE): Move to ...
	* dv-bfin_ebiu_amc.h (BF{IN,50X,54X}_MMR_EBIU_AMC_SIZE): Move to ...
	* dv-bfin_ebiu_ddrc.h (BFIN_MMR_EBIU_DDRC_SIZE): Move to ...
	* dv-bfin_ebiu_sdc.h (BFIN_MMR_EBIU_SDC_SIZE): Move to ...
	* dv-bfin_emac.h (BFIN_MMR_EMAC_{BASE,SIZE}): Move to ...
	* dv-bfin_eppi.h (BFIN_MMR_EPPI_SIZE): Move to ...
	* dv-bfin_evt.h (BFIN_COREMMR_EVT_{BASE,SIZE}): Move to ...
	* dv-bfin_gpio.h (BFIN_MMR_GPIO_SIZE): Move to ...
	* dv-bfin_gptimer.h (BFIN_MMR_GPTIMER_SIZE): Move to ...
	* dv-bfin_jtag.h (BFIN_COREMMR_JTAG_{BASE,SIZE}): Move to ...
	* dv-bfin_mmu.h (BFIN_COREMMR_MMU_{BASE,SIZE}): Move to ...
	* dv-bfin_nfc.h (BFIN_MMR_NFC_SIZE): Move to ...
	* dv-bfin_otp.h (BFIN_MMR_OTP_SIZE): Move to ...
	* dv-bfin_pfmon.h (BFIN_COREMMR_PFMON_{BASE,SIZE}): Move to ...
	* dv-bfin_pll.h (BFIN_MMR_PLL_{BASE,SIZE}): Move to ...
	* dv-bfin_ppi.h (BFIN_MMR_PPI_SIZE): Move to ...
	* dv-bfin_rtc.h (BFIN_MMR_RTC_SIZE): Move to ...
	* dv-bfin_sic.h (BFIN_MMR_SIC_{BASE,SIZE}): Move to ...
	* dv-bfin_spi.h (BFIN_MMR_SPI_SIZE): Move to ...
	* dv-bfin_trace.h (BFIN_COREMMR_TRACE_{BASE,SIZE}): Move to ...
	* dv-bfin_twi.h (BFIN_MMR_TWI_SIZE): Move to ...
	* dv-bfin_uart.h (BFIN_MMR_UART_SIZE): Move to ...
	* dv-bfin_uart2.h (BFIN_MMR_UART2_SIZE): Move to ...
	* dv-bfin_wdog.h (BFIN_MMR_WDOG_SIZE): Move to ...
	* dv-bfin_wp.h (BFIN_COREMMR_WP_{BASE,SIZE}): Move to ...
	* machs.h: ... here.
	* machs.c: Delete all dv-bfin_*.h includes except for cec/dmac.
---
 sim/bfin/dv-bfin_cec.h       |    3 --
 sim/bfin/dv-bfin_ctimer.h    |    3 --
 sim/bfin/dv-bfin_dma.h       |    2 -
 sim/bfin/dv-bfin_dmac.h      |    3 --
 sim/bfin/dv-bfin_ebiu_amc.h  |    4 ---
 sim/bfin/dv-bfin_ebiu_ddrc.h |    2 -
 sim/bfin/dv-bfin_ebiu_sdc.h  |    2 -
 sim/bfin/dv-bfin_emac.h      |    3 --
 sim/bfin/dv-bfin_eppi.h      |    3 --
 sim/bfin/dv-bfin_evt.h       |    3 --
 sim/bfin/dv-bfin_gpio.h      |    3 --
 sim/bfin/dv-bfin_gptimer.h   |    3 --
 sim/bfin/dv-bfin_jtag.h      |    3 --
 sim/bfin/dv-bfin_mmu.h       |    3 --
 sim/bfin/dv-bfin_nfc.h       |    3 --
 sim/bfin/dv-bfin_otp.h       |    6 -----
 sim/bfin/dv-bfin_pfmon.h     |    3 --
 sim/bfin/dv-bfin_pll.h       |    3 --
 sim/bfin/dv-bfin_ppi.h       |    3 --
 sim/bfin/dv-bfin_rtc.h       |    2 -
 sim/bfin/dv-bfin_sic.h       |    3 --
 sim/bfin/dv-bfin_spi.h       |    3 --
 sim/bfin/dv-bfin_trace.h     |    3 --
 sim/bfin/dv-bfin_twi.h       |    3 --
 sim/bfin/dv-bfin_uart.h      |    3 --
 sim/bfin/dv-bfin_uart2.h     |    3 --
 sim/bfin/dv-bfin_wdog.h      |    2 -
 sim/bfin/dv-bfin_wp.h        |    3 --
 sim/bfin/machs.c             |   26 -----------------------
 sim/bfin/machs.h             |   47 ++++++++++++++++++++++++++++++++++++++++++
 30 files changed, 47 insertions(+), 109 deletions(-)

diff --git a/sim/bfin/dv-bfin_cec.h b/sim/bfin/dv-bfin_cec.h
index 027c893..5960da2 100644
--- a/sim/bfin/dv-bfin_cec.h
+++ b/sim/bfin/dv-bfin_cec.h
@@ -23,9 +23,6 @@
 
 #include "sim-main.h"
 
-#define BFIN_COREMMR_CEC_BASE	0xFFE02100
-#define BFIN_COREMMR_CEC_SIZE	(4 * 5)
-
 /* 0xFFE02100 ... 0xFFE02110 */
 #define BFIN_COREMMR_EVT_OVERRIDE	(BFIN_COREMMR_CEC_BASE + (4 * 0))
 #define BFIN_COREMMR_IMASK		(BFIN_COREMMR_CEC_BASE + (4 * 1))
diff --git a/sim/bfin/dv-bfin_ctimer.h b/sim/bfin/dv-bfin_ctimer.h
index c097588..0cfda01 100644
--- a/sim/bfin/dv-bfin_ctimer.h
+++ b/sim/bfin/dv-bfin_ctimer.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_CTIMER_H
 #define DV_BFIN_CTIMER_H
 
-#define BFIN_COREMMR_CTIMER_BASE	0xFFE03000
-#define BFIN_COREMMR_CTIMER_SIZE	(4 * 4)
-
 /* TCNTL Masks */
 #define TMPWR		(1 << 0)
 #define TMREN		(1 << 1)
diff --git a/sim/bfin/dv-bfin_dma.h b/sim/bfin/dv-bfin_dma.h
index 03d412b..bf82869 100644
--- a/sim/bfin/dv-bfin_dma.h
+++ b/sim/bfin/dv-bfin_dma.h
@@ -21,8 +21,6 @@
 #ifndef DV_BFIN_DMA_H
 #define DV_BFIN_DMA_H
 
-#define BFIN_MMR_DMA_SIZE	(4 * 16)
-
 /* DMA_CONFIG Masks */
 #define DMAEN		0x0001	/* DMA Channel Enable */
 #define WNR		0x0002	/* Channel Direction (W/R*) */
diff --git a/sim/bfin/dv-bfin_dmac.h b/sim/bfin/dv-bfin_dmac.h
index dfe9535..33fd829 100644
--- a/sim/bfin/dv-bfin_dmac.h
+++ b/sim/bfin/dv-bfin_dmac.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_DMAC_H
 #define DV_BFIN_DMAC_H
 
-#define BFIN_MMR_DMAC0_BASE	0xFFC00C00
-#define BFIN_MMR_DMAC1_BASE	0xFFC01C00
-
 #define BFIN_DMAC_MDMA_BASE	0x100
 
 struct hw *bfin_dmac_get_peer (struct hw *dma, bu16 pmap);
diff --git a/sim/bfin/dv-bfin_ebiu_amc.h b/sim/bfin/dv-bfin_ebiu_amc.h
index e47fd11..c4f726b 100644
--- a/sim/bfin/dv-bfin_ebiu_amc.h
+++ b/sim/bfin/dv-bfin_ebiu_amc.h
@@ -22,10 +22,6 @@
 #ifndef DV_BFIN_EBIU_AMC_H
 #define DV_BFIN_EBIU_AMC_H
 
-#define BFIN_MMR_EBIU_AMC_SIZE	(4 * 3)
-#define BF50X_MMR_EBIU_AMC_SIZE	0x28
-#define BF54X_MMR_EBIU_AMC_SIZE	(4 * 7)
-
 #define BFIN_EBIU_AMC_BASE	0x20000000
 
 #endif
diff --git a/sim/bfin/dv-bfin_ebiu_ddrc.h b/sim/bfin/dv-bfin_ebiu_ddrc.h
index ac970bf..d60362b 100644
--- a/sim/bfin/dv-bfin_ebiu_ddrc.h
+++ b/sim/bfin/dv-bfin_ebiu_ddrc.h
@@ -21,6 +21,4 @@
 #ifndef DV_BFIN_EBIU_DDRC_H
 #define DV_BFIN_EBIU_DDRC_H
 
-#define BFIN_MMR_EBIU_DDRC_SIZE	0xb0
-
 #endif
diff --git a/sim/bfin/dv-bfin_ebiu_sdc.h b/sim/bfin/dv-bfin_ebiu_sdc.h
index 7849806..967b2bf 100644
--- a/sim/bfin/dv-bfin_ebiu_sdc.h
+++ b/sim/bfin/dv-bfin_ebiu_sdc.h
@@ -21,8 +21,6 @@
 #ifndef DV_BFIN_EBIU_SDC_H
 #define DV_BFIN_EBIU_SDC_H
 
-#define BFIN_MMR_EBIU_SDC_SIZE	(4 * 4)
-
 /* EBIU_SDBCTL Masks */
 #define EBE		0x0001	/* Enable SDRAM External Bank */
 #define EBSZ_16		0x0000	/* Size = 16MB */
diff --git a/sim/bfin/dv-bfin_emac.h b/sim/bfin/dv-bfin_emac.h
index 2522292..b909fb6 100644
--- a/sim/bfin/dv-bfin_emac.h
+++ b/sim/bfin/dv-bfin_emac.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_EMAC_H
 #define DV_BFIN_EMAC_H
 
-#define BFIN_MMR_EMAC_BASE	0xFFC03000
-#define BFIN_MMR_EMAC_SIZE	0x200
-
 /* EMAC_OPMODE Masks */
 #define RE		(1 << 0)
 #define ASTP		(1 << 1)
diff --git a/sim/bfin/dv-bfin_eppi.h b/sim/bfin/dv-bfin_eppi.h
index 1856800..6fada16 100644
--- a/sim/bfin/dv-bfin_eppi.h
+++ b/sim/bfin/dv-bfin_eppi.h
@@ -24,7 +24,4 @@
 
 #include "dv-bfin_ppi.h"
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_EPPI_SIZE	0x40
-
 #endif
diff --git a/sim/bfin/dv-bfin_evt.h b/sim/bfin/dv-bfin_evt.h
index defa082..28a36ea 100644
--- a/sim/bfin/dv-bfin_evt.h
+++ b/sim/bfin/dv-bfin_evt.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_EVT_H
 #define DV_BFIN_EVT_H
 
-#define BFIN_COREMMR_EVT_BASE	0xFFE02000
-#define BFIN_COREMMR_EVT_SIZE	(4 * 16)
-
 extern void cec_set_evt (SIM_CPU *, int ivg, bu32 handler_addr);
 extern bu32 cec_get_evt (SIM_CPU *, int ivg);
 extern bu32 cec_get_reset_evt (SIM_CPU *);
diff --git a/sim/bfin/dv-bfin_gpio.h b/sim/bfin/dv-bfin_gpio.h
index c73ca35..e41b011 100644
--- a/sim/bfin/dv-bfin_gpio.h
+++ b/sim/bfin/dv-bfin_gpio.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_GPIO_H
 #define DV_BFIN_GPIO_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_GPIO_SIZE	(17 * 4)
-
 #endif
diff --git a/sim/bfin/dv-bfin_gptimer.h b/sim/bfin/dv-bfin_gptimer.h
index 2c7c149..75a7a83 100644
--- a/sim/bfin/dv-bfin_gptimer.h
+++ b/sim/bfin/dv-bfin_gptimer.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_GPTIMER_H
 #define DV_BFIN_GPTIMER_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_GPTIMER_SIZE	(4 * 4)
-
 #endif
diff --git a/sim/bfin/dv-bfin_jtag.h b/sim/bfin/dv-bfin_jtag.h
index 65c1d3b..9ed62b3 100644
--- a/sim/bfin/dv-bfin_jtag.h
+++ b/sim/bfin/dv-bfin_jtag.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_JTAG_H
 #define DV_BFIN_JTAG_H
 
-#define BFIN_COREMMR_JTAG_BASE	0xFFE05000
-#define BFIN_COREMMR_JTAG_SIZE	(4 * 3)
-
 #endif
diff --git a/sim/bfin/dv-bfin_mmu.h b/sim/bfin/dv-bfin_mmu.h
index e03a327..b86a145 100644
--- a/sim/bfin/dv-bfin_mmu.h
+++ b/sim/bfin/dv-bfin_mmu.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_MMU_H
 #define DV_BFIN_MMU_H
 
-#define BFIN_COREMMR_MMU_BASE	0xFFE00000
-#define BFIN_COREMMR_MMU_SIZE	0x2000
-
 void mmu_check_addr (SIM_CPU *, bu32 addr, bool write, bool inst, int size);
 void mmu_check_cache_addr (SIM_CPU *, bu32 addr, bool write, bool inst);
 void mmu_process_fault (SIM_CPU *, bu32 addr, bool write, bool inst, bool unaligned, bool miss);
diff --git a/sim/bfin/dv-bfin_nfc.h b/sim/bfin/dv-bfin_nfc.h
index 42dbec6..8c8a139 100644
--- a/sim/bfin/dv-bfin_nfc.h
+++ b/sim/bfin/dv-bfin_nfc.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_NFC_H
 #define DV_BFIN_NFC_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_NFC_SIZE	0x50
-
 /* NFC_STAT masks.  */
 #define NBUSY		(1 << 0)
 #define WB_FULL		(1 << 1)
diff --git a/sim/bfin/dv-bfin_otp.h b/sim/bfin/dv-bfin_otp.h
index bbb49ce..3a0f5d0 100644
--- a/sim/bfin/dv-bfin_otp.h
+++ b/sim/bfin/dv-bfin_otp.h
@@ -21,12 +21,6 @@
 #ifndef DV_BFIN_OTP_H
 #define DV_BFIN_OTP_H
 
-/* XXX: This should be pushed into the model data.  */
-/* XXX: Not exactly true; it's two sets of 4 regs near each other:
-          0xFFC03600 0x10 - Control
-          0xFFC03680 0x10 - Data  */
-#define BFIN_MMR_OTP_SIZE	0xa0
-
 /* OTP Defined Pages.  */
 #define FPS00		0x004
 #define FPS01		0x005
diff --git a/sim/bfin/dv-bfin_pfmon.h b/sim/bfin/dv-bfin_pfmon.h
index 27a216e..cd2e6df 100644
--- a/sim/bfin/dv-bfin_pfmon.h
+++ b/sim/bfin/dv-bfin_pfmon.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_PFMON_H
 #define DV_BFIN_PFMON_H
 
-#define BFIN_COREMMR_PFMON_BASE	0xFFE08000
-#define BFIN_COREMMR_PFMON_SIZE	0x108
-
 #endif
diff --git a/sim/bfin/dv-bfin_pll.h b/sim/bfin/dv-bfin_pll.h
index b63104a..7e2bfb5 100644
--- a/sim/bfin/dv-bfin_pll.h
+++ b/sim/bfin/dv-bfin_pll.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_PLL_H
 #define DV_BFIN_PLL_H
 
-#define BFIN_MMR_PLL_BASE	0xFFC00000
-#define BFIN_MMR_PLL_SIZE	(4 * 6)
-
 #endif
diff --git a/sim/bfin/dv-bfin_ppi.h b/sim/bfin/dv-bfin_ppi.h
index 24e8fd9..b086ef7 100644
--- a/sim/bfin/dv-bfin_ppi.h
+++ b/sim/bfin/dv-bfin_ppi.h
@@ -22,9 +22,6 @@
 #ifndef DV_BFIN_PPI_H
 #define DV_BFIN_PPI_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_PPI_SIZE	(4 * 5)
-
 /* PPI_CONTROL Masks.  */
 #define PORT_EN		(1 << 0)
 #define PORT_DIR	(1 << 1)
diff --git a/sim/bfin/dv-bfin_rtc.h b/sim/bfin/dv-bfin_rtc.h
index 04ffde1..f3d62aa 100644
--- a/sim/bfin/dv-bfin_rtc.h
+++ b/sim/bfin/dv-bfin_rtc.h
@@ -21,6 +21,4 @@
 #ifndef DV_BFIN_RTC_H
 #define DV_BFIN_RTC_H
 
-#define BFIN_MMR_RTC_SIZE	(4 * 6)
-
 #endif
diff --git a/sim/bfin/dv-bfin_sic.h b/sim/bfin/dv-bfin_sic.h
index e70a749..5c953bc 100644
--- a/sim/bfin/dv-bfin_sic.h
+++ b/sim/bfin/dv-bfin_sic.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_SIC_H
 #define DV_BFIN_SIC_H
 
-#define BFIN_MMR_SIC_BASE	0xFFC00100
-#define BFIN_MMR_SIC_SIZE	0x100
-
 #endif
diff --git a/sim/bfin/dv-bfin_spi.h b/sim/bfin/dv-bfin_spi.h
index 5e216bf..cdcba80 100644
--- a/sim/bfin/dv-bfin_spi.h
+++ b/sim/bfin/dv-bfin_spi.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_SPI_H
 #define DV_BFIN_SPI_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_SPI_SIZE	(4 * 7)
-
 /* SPI_CTL Masks.  */
 #define TIMOD		(3 << 0)
 #define RDBR_CORE	(0 << 0)
diff --git a/sim/bfin/dv-bfin_trace.h b/sim/bfin/dv-bfin_trace.h
index 3acfddf..05f6701 100644
--- a/sim/bfin/dv-bfin_trace.h
+++ b/sim/bfin/dv-bfin_trace.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_TRACE_H
 #define DV_BFIN_TRACE_H
 
-#define BFIN_COREMMR_TRACE_BASE	0xFFE06000
-#define BFIN_COREMMR_TRACE_SIZE	(4 * 65)
-
 /* TBUFCTL Masks */
 #define TBUFPWR			0x0001
 #define TBUFEN			0x0002
diff --git a/sim/bfin/dv-bfin_twi.h b/sim/bfin/dv-bfin_twi.h
index a31df78..5c195d5 100644
--- a/sim/bfin/dv-bfin_twi.h
+++ b/sim/bfin/dv-bfin_twi.h
@@ -21,9 +21,6 @@
 #ifndef DV_BFIN_TWI_H
 #define DV_BFIN_TWI_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_TWI_SIZE	0x90
-
 /* TWI_MASTER_STAT Masks */
 #define MPROG		(1 << 0)
 #define LOSTARB		(1 << 1)
diff --git a/sim/bfin/dv-bfin_uart.h b/sim/bfin/dv-bfin_uart.h
index 52074f6..a7e106a 100644
--- a/sim/bfin/dv-bfin_uart.h
+++ b/sim/bfin/dv-bfin_uart.h
@@ -22,9 +22,6 @@
 #ifndef DV_BFIN_UART_H
 #define DV_BFIN_UART_H
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_UART_SIZE	0x30
-
 struct bfin_uart;
 bu16 bfin_uart_get_next_byte (struct hw *, bu16, bu16, bool *fresh);
 bu16 bfin_uart_write_byte (struct hw *, bu16, bu16);
diff --git a/sim/bfin/dv-bfin_uart2.h b/sim/bfin/dv-bfin_uart2.h
index f8269a4..2ad9736 100644
--- a/sim/bfin/dv-bfin_uart2.h
+++ b/sim/bfin/dv-bfin_uart2.h
@@ -24,9 +24,6 @@
 
 #include "dv-bfin_uart.h"
 
-/* XXX: This should be pushed into the model data.  */
-#define BFIN_MMR_UART2_SIZE	0x30
-
 /* UART_MSR */
 #define SCTS (1 << 0)
 
diff --git a/sim/bfin/dv-bfin_wdog.h b/sim/bfin/dv-bfin_wdog.h
index 9be602d..915bb07 100644
--- a/sim/bfin/dv-bfin_wdog.h
+++ b/sim/bfin/dv-bfin_wdog.h
@@ -21,8 +21,6 @@
 #ifndef DV_BFIN_WDOG_H
 #define DV_BFIN_WDOG_H
 
-#define BFIN_MMR_WDOG_SIZE	(4 * 3)
-
 /* WDOG_CTL */
 #define WDEV            0x0006  /* event generated on roll over */
 #define WDEV_RESET      0x0000  /* generate reset event on roll over */
diff --git a/sim/bfin/dv-bfin_wp.h b/sim/bfin/dv-bfin_wp.h
index f6c0d80..1d4135b 100644
--- a/sim/bfin/dv-bfin_wp.h
+++ b/sim/bfin/dv-bfin_wp.h
@@ -21,7 +21,4 @@
 #ifndef DV_BFIN_WP_H
 #define DV_BFIN_WP_H
 
-#define BFIN_COREMMR_WP_BASE	0xFFE07000
-#define BFIN_COREMMR_WP_SIZE	0x204
-
 #endif
diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c
index f6534f5..5e3b68e 100644
--- a/sim/bfin/machs.c
+++ b/sim/bfin/machs.c
@@ -27,33 +27,7 @@
 #include "sim-hw.h"
 #include "devices.h"
 #include "dv-bfin_cec.h"
-#include "dv-bfin_ctimer.h"
-#include "dv-bfin_dma.h"
 #include "dv-bfin_dmac.h"
-#include "dv-bfin_ebiu_amc.h"
-#include "dv-bfin_ebiu_ddrc.h"
-#include "dv-bfin_ebiu_sdc.h"
-#include "dv-bfin_emac.h"
-#include "dv-bfin_eppi.h"
-#include "dv-bfin_evt.h"
-#include "dv-bfin_gpio.h"
-#include "dv-bfin_gptimer.h"
-#include "dv-bfin_jtag.h"
-#include "dv-bfin_mmu.h"
-#include "dv-bfin_nfc.h"
-#include "dv-bfin_otp.h"
-#include "dv-bfin_pfmon.h"
-#include "dv-bfin_pll.h"
-#include "dv-bfin_ppi.h"
-#include "dv-bfin_rtc.h"
-#include "dv-bfin_sic.h"
-#include "dv-bfin_spi.h"
-#include "dv-bfin_trace.h"
-#include "dv-bfin_twi.h"
-#include "dv-bfin_uart.h"
-#include "dv-bfin_uart2.h"
-#include "dv-bfin_wdog.h"
-#include "dv-bfin_wp.h"
 
 static const MACH bfin_mach;
 
diff --git a/sim/bfin/machs.h b/sim/bfin/machs.h
index ac16adb..1723ded 100644
--- a/sim/bfin/machs.h
+++ b/sim/bfin/machs.h
@@ -53,4 +53,51 @@ enum {
   BFIN_INSN_MAX
 };
 
+#define BFIN_COREMMR_CEC_BASE		0xFFE02100
+#define BFIN_COREMMR_CEC_SIZE		(4 * 5)
+#define BFIN_COREMMR_CTIMER_BASE	0xFFE03000
+#define BFIN_COREMMR_CTIMER_SIZE	(4 * 4)
+#define BFIN_COREMMR_EVT_BASE		0xFFE02000
+#define BFIN_COREMMR_EVT_SIZE		(4 * 16)
+#define BFIN_COREMMR_JTAG_BASE		0xFFE05000
+#define BFIN_COREMMR_JTAG_SIZE		(4 * 3)
+#define BFIN_COREMMR_MMU_BASE		0xFFE00000
+#define BFIN_COREMMR_MMU_SIZE		0x2000
+#define BFIN_COREMMR_PFMON_BASE		0xFFE08000
+#define BFIN_COREMMR_PFMON_SIZE		0x108
+#define BFIN_COREMMR_TRACE_BASE		0xFFE06000
+#define BFIN_COREMMR_TRACE_SIZE		(4 * 65)
+#define BFIN_COREMMR_WP_BASE		0xFFE07000
+#define BFIN_COREMMR_WP_SIZE		0x204
+
+#define BFIN_MMR_DMA_SIZE		(4 * 16)
+#define BFIN_MMR_DMAC0_BASE		0xFFC00C00
+#define BFIN_MMR_DMAC1_BASE		0xFFC01C00
+#define BFIN_MMR_EBIU_AMC_SIZE		(4 * 3)
+#define BF50X_MMR_EBIU_AMC_SIZE		0x28
+#define BF54X_MMR_EBIU_AMC_SIZE		(4 * 7)
+#define BFIN_MMR_EBIU_DDRC_SIZE		0xb0
+#define BFIN_MMR_EBIU_SDC_SIZE		(4 * 4)
+#define BFIN_MMR_EMAC_BASE		0xFFC03000
+#define BFIN_MMR_EMAC_SIZE		0x200
+#define BFIN_MMR_EPPI_SIZE		0x40
+#define BFIN_MMR_GPIO_SIZE		(17 * 4)
+#define BFIN_MMR_GPTIMER_SIZE		(4 * 4)
+#define BFIN_MMR_NFC_SIZE		0x50
+/* XXX: Not exactly true; it's two sets of 4 regs near each other:
+          0xFFC03600 0x10 - Control
+          0xFFC03680 0x10 - Data  */
+#define BFIN_MMR_OTP_SIZE		0xa0
+#define BFIN_MMR_PLL_BASE		0xFFC00000
+#define BFIN_MMR_PLL_SIZE		(4 * 6)
+#define BFIN_MMR_PPI_SIZE		(4 * 5)
+#define BFIN_MMR_RTC_SIZE		(4 * 6)
+#define BFIN_MMR_SIC_BASE		0xFFC00100
+#define BFIN_MMR_SIC_SIZE		0x100
+#define BFIN_MMR_SPI_SIZE		(4 * 7)
+#define BFIN_MMR_TWI_SIZE		0x90
+#define BFIN_MMR_WDOG_SIZE		(4 * 3)
+#define BFIN_MMR_UART_SIZE		0x30
+#define BFIN_MMR_UART2_SIZE		0x30
+
 #endif
-- 
1.7.5.rc3
Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]