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Thanks, Swami
--- Begin Message ---Hello,
- From: "M R Swami Reddy" <MR dot Swami dot Reddy at nsc dot com>
- To: gdb-patches at sourceware dot org
- Date: Fri, 02 May 2008 17:00:29 +0530
- Subject: [PATCH] CR16 target simulator specific patch
Updated CR16 target specific machine code decoding algorithm using hash table and added a few test cases to testsuite/sim/cr16 directory.
Please find the attached patch for the above changes.
Ran the simulator tests and test summary as shown below: ======================= === sim Summary === # of expected passes 130 cr16-elf-run 0.5
make[2]: Leaving directory `/home10/swami/src/gdb/build/sim/testsuite' make[1]: Leaving directory `/home10/swami/src/gdb/build/sim' ==============
OK to commit?
Thanks, SwamiIndex: ChangeLog =================================================================== RCS file: /cvs/src/src/sim/cr16/ChangeLog,v retrieving revision 1.1 diff -c -u -a -r1.1 ChangeLog --- ChangeLog 8 Apr 2008 09:20:06 -0000 1.1 +++ ChangeLog 2 May 2008 11:07:36 -0000 @@ -1,3 +1,9 @@ +2008-05-02 M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> + + * interp.c: Update the machine code decode algorithm using hash table. + * Makefile.in, cr16_sim.h, gencode.c and simops.c: Update for typos + and coding standards. + 2008-02-12 M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> * ChangeLog, Makefile.in, configure, configure.in, cr16_sim.h, Index: Makefile.in =================================================================== RCS file: /cvs/src/src/sim/cr16/Makefile.in,v retrieving revision 1.1 diff -c -u -a -r1.1 Makefile.in --- Makefile.in 8 Apr 2008 09:20:06 -0000 1.1 +++ Makefile.in 2 May 2008 11:07:36 -0000 @@ -1,6 +1,6 @@ -# Makefile template for Configure for the D10v sim library. -# Copyright (C) 1996, 1997 Free Software Foundation, Inc. -# Written by Cygnus Support. +# Makefile template for Configure for the CR16 sim library. +# Copyright (C) 2008 Free Software Foundation, Inc. +# Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by Index: cr16_sim.h =================================================================== RCS file: /cvs/src/src/sim/cr16/cr16_sim.h,v retrieving revision 1.1 diff -c -u -a -r1.1 cr16_sim.h --- cr16_sim.h 8 Apr 2008 09:20:06 -0000 1.1 +++ cr16_sim.h 2 May 2008 11:07:36 -0000 @@ -14,8 +14,9 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License along - with this program. If not, see <http://www.gnu.org/licenses/>. */ + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + #include "config.h" #include <stdio.h> @@ -59,15 +60,15 @@ struct simops { - char mnimonic[6]; - int size; // size - long mask; - long opcode; + char mnimonic[12]; + uint32 size; + uint32 mask; + uint32 opcode; int format; - char fname[10]; + char fname[12]; void (*func)(); int numops; - int operands[4]; + operand_desc operands[4]; }; enum _ins_type @@ -309,13 +310,13 @@ PSR_I_BIT = 0x0800, PSR_P_BIT = 0x0400, PSR_E_BIT = 0x0200, - PSR_N_BIT = 0x0100, + PSR_N_BIT = 0x0080, PSR_Z_BIT = 0x0040, PSR_F_BIT = 0x0020, - PSR_U_BIT = 0x0010, + PSR_U_BIT = 0x0008, PSR_L_BIT = 0x0004, PSR_T_BIT = 0x0002, - PSR_C_BIT = 0x0001, + PSR_C_BIT = 0x0001 }; #define PSR CREG (PSR_CR) Index: endian.c =================================================================== RCS file: /cvs/src/src/sim/cr16/endian.c,v retrieving revision 1.1 diff -c -u -a -r1.1 endian.c --- endian.c 8 Apr 2008 09:20:06 -0000 1.1 +++ endian.c 2 May 2008 11:07:36 -0000 @@ -14,8 +14,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License along - with this program. If not, see <http://www.gnu.org/licenses/>. */ + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* If we're being compiled as a .c file, rather than being included in Index: gencode.c =================================================================== RCS file: /cvs/src/src/sim/cr16/gencode.c,v retrieving revision 1.1 diff -c -u -a -r1.1 gencode.c --- gencode.c 8 Apr 2008 09:20:06 -0000 1.1 +++ gencode.c 2 May 2008 11:07:36 -0000 @@ -14,8 +14,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License along - with this program. If not, see <http://www.gnu.org/licenses/>. */ + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "config.h" @@ -30,9 +30,7 @@ static void write_template PARAMS ((void)); int -main (argc, argv) - int argc; - char *argv[]; +main (int argc, char *argv[]) { if ((argc > 1) && (strcmp (argv[1],"-h") == 0)) write_header(); @@ -60,8 +58,8 @@ } -/* write_template creates a file all required functions, ready */ -/* to be filled out */ +/* write_template creates a file all required functions, + ready to be filled out. */ static void write_template () @@ -74,37 +72,37 @@ for ( ; i < NUMOPCODES; i++) { if (cr16_instruction[i].size != 0) - { - printf("/* %s */\nvoid\nOP_%X_%X ()\n{\n",cr16_instruction[i].mnemonic,cr16_instruction[i].match,(32 - cr16_instruction[i].match_bits)); - - /* count operands */ - j = 0; - for (k=0;k<5;k++) - { - if (cr16_instruction[i].operands[k].op_type == dummy) +{ + printf("/* %s */\nvoid\nOP_%X_%X ()\n{\n",cr16_instruction[i].mnemonic,cr16_instruction[i].match,(32 - cr16_instruction[i].match_bits)); + + /* count operands. */ + j = 0; + for (k=0;k<5;k++) + { + if (cr16_instruction[i].operands[k].op_type == dummy) break; else j++; - } - switch (j) - { - case 0: - printf ("printf(\" %s\\n\");\n",cr16_instruction[i].mnemonic); - break; - case 1: - printf ("printf(\" %s\\t%%x\\n\",OP[0]);\n",cr16_instruction[i].mnemonic); - break; - case 2: - printf ("printf(\" %s\\t%%x,%%x\\n\",OP[0],OP[1]);\n",cr16_instruction[i].mnemonic); - break; - case 3: - printf ("printf(\" %s\\t%%x,%%x,%%x\\n\",OP[0],OP[1],OP[2]);\n",cr16_instruction[i].mnemonic); - break; - default: - fprintf (stderr,"Too many operands: %d\n",j); - } - printf ("}\n\n"); - } + } + switch (j) + { + case 0: + printf ("printf(\" %s\\n\");\n",cr16_instruction[i].mnemonic); + break; + case 1: + printf ("printf(\" %s\\t%%x\\n\",OP[0]);\n",cr16_instruction[i].mnemonic); + break; + case 2: + printf ("printf(\" %s\\t%%x,%%x\\n\",OP[0],OP[1]);\n",cr16_instruction[i].mnemonic); + break; + case 3: + printf ("printf(\" %s\\t%%x,%%x,%%x\\n\",OP[0],OP[1],OP[2]);\n",cr16_instruction[i].mnemonic); + break; + default: + fprintf (stderr,"Too many operands: %d\n",j); + } + printf ("}\n\n"); +} } } @@ -127,56 +125,50 @@ { int i = 0, j = 0, k; - unsigned long mask; - /* write out opcode table */ + /* write out opcode table. */ printf ("#include \"cr16_sim.h\"\n"); printf ("#include \"simops.h\"\n\n"); printf ("struct simops Simops[] = {\n"); - for ( ; i < NUMOPCODES; i++) + for (i = NUMOPCODES-1; i >= 0; --i) { if (cr16_instruction[i].size != 0) - { +{ printf (" { \"%s\", %ld, %d, %d, %d, \"OP_%X_%X\", OP_%X_%X, ", cr16_instruction[i].mnemonic, cr16_instruction[i].size, cr16_instruction[i].match_bits, cr16_instruction[i].match, cr16_instruction[i].flags, ((BIN(cr16_instruction[i].match, cr16_instruction[i].match_bits))>>(cr16_instruction[i].match_bits)), - (32 - cr16_instruction[i].match_bits), + (32 - cr16_instruction[i].match_bits), ((BIN(cr16_instruction[i].match, cr16_instruction[i].match_bits))>>(cr16_instruction[i].match_bits)), (32 - cr16_instruction[i].match_bits)); - j = 0; - for (k=0;k<5;k++) - { - if (cr16_instruction[i].operands[k].op_type == dummy) + j = 0; + for (k=0;k<5;k++) + { + if (cr16_instruction[i].operands[k].op_type == dummy) break; else j++; - } - printf ("%d, ",j); - - j = 0; - for (k=0;k<4;k++) - { - int flags = cr16_instruction[i].operands[k].op_type; - int match_bits = cr16_instruction[i].operands[k].shift; - { - if (j == 0) - printf ("{"); - else - printf (", "); - // if (cr16_instruction[i].size == 2) - // match_bits += 15; - printf ("{"); - printf ("%d,%d",cr16_instruction[i].operands[k].shift,flags); - printf ("}"); - j = 1; - } - } - if (j) - printf ("}"); - printf ("},\n"); - } } - //printf (" { 0,0,0,0,(void (*)(void))0,0,{0,0,0}},\n};\n"); + printf ("%d, ",j); + + j = 0; + for (k=0;k<4;k++) + { + int optype = cr16_instruction[i].operands[k].op_type; + int shift = cr16_instruction[i].operands[k].shift; + if (j == 0) + printf ("{"); + else + printf (", "); + printf ("{"); + printf ("%d,%d",optype, shift); + printf ("}"); + j = 1; + } + if (j) + printf ("}"); + printf ("},\n"); + } + } printf (" { \"NULL\",1,8,0,0,\"OP_0_20\",OP_0_20,0,{0,0,0}},\n};\n"); } Index: interp.c =================================================================== RCS file: /cvs/src/src/sim/cr16/interp.c,v retrieving revision 1.1 diff -c -u -a -r1.1 interp.c --- interp.c 8 Apr 2008 09:20:06 -0000 1.1 +++ interp.c 2 May 2008 11:07:36 -0000 @@ -14,8 +14,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License along - with this program. If not, see <http://www.gnu.org/licenses/>. */ + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <signal.h> #include "sysdep.h" @@ -28,7 +28,7 @@ #include "gdb/signals.h" #include "opcode/cr16.h" -enum _leftright { LEFT_FIRST, RIGHT_FIRST }; +//enum _leftright { LEFT_FIRST, RIGHT_FIRST }; static char *myname; static SIM_OPEN_KIND sim_kind; @@ -52,8 +52,11 @@ bfd_vma text_start; bfd_vma text_end; -static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize)); -static void do_run PARAMS ((inst *ins, uint64 mc)); +static long hash PARAMS ((uint64 linsn, int)); +static struct hash_entry *lookup_hash PARAMS ((uint64 ins, int size)); +static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize, int nops)); +//static void do_run PARAMS ((inst *ins, uint64 mc)); +static int do_run PARAMS ((uint64 mc)); static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value)); extern void sim_set_profile PARAMS ((int n)); extern void sim_set_profile_size PARAMS ((int n)); @@ -77,9 +80,72 @@ #define INLINE #endif #endif +#define MAX_HASH 16 + +struct hash_entry +{ + struct hash_entry *next; + uint32 opcode; + uint32 mask; + int format; + int size; + struct simops *ops; +}; + +struct hash_entry hash_table[MAX_HASH+1]; + +INLINE static long +hash(unsigned long long insn, int format) +{ + unsigned int i = 4, tmp; + if (format) + { + while ((insn >> i) != 0) i +=4; + + return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key. */ + } + return ((insn & 0xF)); /* Use last 4 bits as hask key. */ +} + + +INLINE static struct hash_entry * +lookup_hash (uint64 ins, int size) +{ + uint32 mask; + struct hash_entry *h; + + h = &hash_table[hash(ins,1)]; + + + mask = (((1 << (32 - h->mask)) -1) << h->mask); + + /* Adjuest mask for branch with 2 word instructions. */ + if ((h->ops->mnimonic != NULL) && + ((streq(h->ops->mnimonic,"b") && h->size == 2))) + mask = 0xff0f0000; + + + while ((ins & mask) != (BIN(h->opcode, h->mask))) + { + if (h->next == NULL) + { + State.exception = SIGILL; + State.pc_changed = 1; /* Don't increment the PC. */ + return NULL; + } + h = h->next; + + mask = (((1 << (32 - h->mask)) -1) << h->mask); + /* Adjuest mask for branch with 2 word instructions. */ + if ((streq(h->ops->mnimonic,"b")) && h->size == 2) + mask = 0xff0f0000; + + } + return (h); +} INLINE static void -get_operands (operand_desc *s, uint64 ins, int isize) +get_operands (operand_desc *s, uint64 ins, int isize, int nops) { uint32 i, opn = 0, start_bit = 0, op_type = 0; int32 op_size = 0, mask = 0; @@ -87,211 +153,215 @@ if (isize == 1) /* Trunkcate the extra 16 bits of INS. */ ins = ins >> 16; - for (i=0; i < 3; ++i,++opn) + for (i=0; i < 4; ++i,++opn) { - if ((s[opn].op_type == dummy) || (s[opn].op_type > cr16_num_optab)) - break; - else - op_type = s[opn].op_type; + if (s[opn].op_type == dummy) break; + op_type = s[opn].op_type; start_bit = s[opn].shift; op_size = cr16_optab[op_type].bit_size; switch (op_type) - { + { case imm3: case imm4: case imm5: case imm6: - { - if (isize == 1) - OP[i] = ((ins >> 4) & ((1 << op_size) -1)); + { + if (isize == 1) + OP[i] = ((ins >> 4) & ((1 << op_size) -1)); else - OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1)); + OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1)); - if (OP[i] & ((long)1 << (op_size -1))) - { - sign_flag = 1; - OP[i] = ~(OP[i]) + 1; - } - OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1)); + if (OP[i] & ((long)1 << (op_size -1))) + { + sign_flag = 1; + OP[i] = ~(OP[i]) + 1; + } + OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1)); } - break; + break; case uimm3: case uimm3_1: case uimm4_1: - if (isize == 1) - OP[i] = ((ins >> 4) & ((1 << op_size) -1)); - else - OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1)); - break; + switch (isize) + { + case 1: + OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break; + case 2: + OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break; + default: /* for case 3. */ + OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break; + break; + } + break; case uimm4: - switch (isize) - { - case 1: - if (start_bit == 20) - OP[i] = ((ins >> 4) & ((1 << op_size) -1)); - else - OP[i] = (ins & ((1 << op_size) -1)); - break; - case 2: - OP[i] = ((ins >> start_bit) & ((1 << op_size) -1)); - break; - case 3: - OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1)); - break; - default: - OP[i] = ((ins >> start_bit) & ((1 << op_size) -1)); - break; - } - break; + switch (isize) + { + case 1: + if (start_bit == 20) + OP[i] = ((ins >> 4) & ((1 << op_size) -1)); + else + OP[i] = (ins & ((1 << op_size) -1)); + break; + case 2: + OP[i] = ((ins >> start_bit) & ((1 << op_size) -1)); + break; + case 3: + OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1)); + break; + default: + OP[i] = ((ins >> start_bit) & ((1 << op_size) -1)); + break; + } + break; case imm16: case uimm16: OP[i] = ins & 0xFFFF; - break; + break; case uimm20: case imm20: - OP[i] = ins & (((long)1 << op_size) - 1); - break; + OP[i] = ins & (((long)1 << op_size) - 1); + break; case imm32: case uimm32: OP[i] = ins & 0xFFFFFFFF; - break; + break; - case uimm5: break; /*NOT USED. */ + case uimm5: break; /*NOT USED. */ OP[i] = ins & ((1 << op_size) - 1); break; case disps5: OP[i] = (ins >> 4) & ((1 << 4) - 1); OP[i] = (OP[i] * 2) + 2; - if (OP[i] & ((long)1 << 5)) - { - sign_flag = 1; - OP[i] = ~(OP[i]) + 1; - OP[i] = (unsigned long int)(OP[i] & 0x1F); - } - break; - - case dispe9: - OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf)); - OP[i] <<= 1; - if (OP[i] & ((long)1 << 8)) - { - sign_flag = 1; - OP[i] = ~(OP[i]) + 1; - OP[i] = (unsigned long int)(OP[i] & 0xFF); - } - break; - - case disps17: - OP[i] = (ins & 0xFFFF); - if (OP[i] & 1) - { - OP[i] = (OP[i] & 0xFFFE); - sign_flag = 1; - OP[i] = ~(OP[i]) + 1; - OP[i] = (unsigned long int)(OP[i] & 0xFFFF); + if (OP[i] & ((long)1 << 5)) + { + sign_flag = 1; + OP[i] = ~(OP[i]) + 1; + OP[i] = (unsigned long int)(OP[i] & 0x1F); + } + break; + + case dispe9: + OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf)); + OP[i] <<= 1; + if (OP[i] & ((long)1 << 8)) + { + sign_flag = 1; + OP[i] = ~(OP[i]) + 1; + OP[i] = (unsigned long int)(OP[i] & 0xFF); + } + break; + + case disps17: + OP[i] = (ins & 0xFFFF); + if (OP[i] & 1) + { + OP[i] = (OP[i] & 0xFFFE); + sign_flag = 1; + OP[i] = ~(OP[i]) + 1; + OP[i] = (unsigned long int)(OP[i] & 0xFFFF); } - break; + break; - case disps25: - if (isize == 2) - OP[i] = (ins & 0xFFFFFF); - else - OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) | - (((ins >> 16) & 0xf) << 20); - - if (OP[i] & 1) - { - OP[i] = (OP[i] & 0xFFFFFE); - sign_flag = 1; - OP[i] = ~(OP[i]) + 1; - OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF); + case disps25: + if (isize == 2) + OP[i] = (ins & 0xFFFFFF); + else + OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) | + (((ins >> 16) & 0xf) << 20); + + if (OP[i] & 1) + { + OP[i] = (OP[i] & 0xFFFFFE); + sign_flag = 1; + OP[i] = ~(OP[i]) + 1; + OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF); } - break; + break; case abs20: - if (isize == 3) + if (isize == 3) OP[i] = (ins) & 0xFFFFF; - else + else OP[i] = (ins >> start_bit) & 0xFFFFF; - break; + break; case abs24: - if (isize == 3) - OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20) - | (((ins >> 24) & 0xf) << 16)); - else - OP[i] = (ins >> 16) & 0xFFFFFF; - break; + if (isize == 3) + OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20) + | (((ins >> 24) & 0xf) << 16)); + else + OP[i] = (ins >> 16) & 0xFFFFFF; + break; case rra: case rbase: break; /* NOT USED. */ case rbase_disps20: case rbase_dispe20: case rpbase_disps20: case rpindex_disps20: - OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF)); - OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ - break; + OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF)); + OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ + break; case rpbase_disps0: - OP[i] = 0; /* 4 bit disp const. */ - OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ - break; + OP[i] = 0; /* 4 bit disp const. */ + OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ + break; case rpbase_dispe4: - OP[i] = ((ins >> 8) & 0xF) * 2; /* 4 bit disp const. */ - OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ - break; + OP[i] = ((ins >> 8) & 0xF) * 2; /* 4 bit disp const. */ + OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ + break; case rpbase_disps4: - OP[i] = ((ins >> 8) & 0xF); /* 4 bit disp const. */ - OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ - break; + OP[i] = ((ins >> 8) & 0xF); /* 4 bit disp const. */ + OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ + break; case rpbase_disps16: - OP[i] = (ins) & 0xFFFF; - OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ - break; + OP[i] = (ins) & 0xFFFF; + OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ + break; case rpindex_disps0: - OP[i] = 0; - OP[++i] = (ins >> 4) & 0xF; /* get 4 bit for reg. */ - OP[++i] = (ins >> 8) & 0x1; /* get 1 bit for index-reg. */ - break; + OP[i] = 0; + OP[++i] = (ins >> 4) & 0xF; /* get 4 bit for reg. */ + OP[++i] = (ins >> 8) & 0x1; /* get 1 bit for index-reg. */ + break; case rpindex_disps14: - OP[i] = (ins) & 0x3FFF; - OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */ - OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ + OP[i] = (ins) & 0x3FFF; + OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */ + OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ case rindex7_abs20: case rindex8_abs20: - OP[i] = (ins) & 0xFFFFF; - OP[++i] = (ins >> 24) & 0x1; /* get 1 bit for index-reg. */ - OP[++i] = (ins >> 20) & 0xF; /* get 4 bit for reg. */ - break; + OP[i] = (ins) & 0xFFFFF; + OP[++i] = (ins >> 24) & 0x1; /* get 1 bit for index-reg. */ + OP[++i] = (ins >> 20) & 0xF; /* get 4 bit for reg. */ + break; case regr: case regp: case pregr: case pregrp: - switch(isize) - { - case 1: - if (start_bit == 20) OP[i] = (ins >> 4) & 0xF; - else if (start_bit == 16) OP[i] = ins & 0xF; - break; - case 2: OP[i] = (ins >> start_bit) & 0xF; break; - case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break; - } - break; + switch(isize) + { + case 1: + if (start_bit == 20) OP[i] = (ins >> 4) & 0xF; + else if (start_bit == 16) OP[i] = ins & 0xF; + break; + case 2: OP[i] = (ins >> start_bit) & 0xF; break; + case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break; + } + break; case cc: - { - if (isize == 1) OP[i] = (ins >> 4) & 0xF; - else if (isize == 2) OP[i] = (ins >> start_bit) & 0xF; - else OP[i] = (ins >> (start_bit + 16)) & 0xF; - break; - } - default: break; - } + { + if (isize == 1) OP[i] = (ins >> 4) & 0xF; + else if (isize == 2) OP[i] = (ins >> start_bit) & 0xF; + else OP[i] = (ins >> (start_bit + 16)) & 0xF; + break; + } + default: break; + } - /* For ESC on uimm4_1 operand */ + /* For ESC on uimm4_1 operand. */ if (op_type == uimm4_1) - if (OP[i] == 9) - OP[i] = -1; + if (OP[i] == 9) + OP[i] = -1; + + /* For increment by 1. */ + if ((op_type == pregr) || (op_type == pregrp)) + OP[i] += 1; } /* FIXME: for tracing, update values that need to be updated each instruction decode cycle */ -#if 0 // DEBUG - (*cr16_callback->printf_filtered) (cr16_callback, "OP0=0x%X\t,OP1=0x%X\t,OP2=0x%X\t,OP3=0X%X\n",OP[0],OP[1],OP[2],OP[3]); -#endif State.trace.psw = PSR; - } bfd_vma @@ -302,13 +372,13 @@ { init_text_p = 1; for (s = prog_bfd->sections; s; s = s->next) - if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0) - { - text = s; - text_start = bfd_get_section_vma (prog_bfd, s); - text_end = text_start + bfd_section_size (prog_bfd, s); - break; - } + if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0) + { + text = s; + text_start = bfd_get_section_vma (prog_bfd, s); + text_end = text_start + bfd_section_size (prog_bfd, s); + break; + } } return (PC) + text_start; @@ -316,35 +386,44 @@ -static void -do_run(inst *instruction, uint64 mcode) +static int +do_run(uint64 mcode) { struct simops *s= Simops; + struct hash_entry *h; char func[12]="\0"; + uint8 *iaddr; #ifdef DEBUG if ((cr16_debug & DEBUG_INSTRUCTION) != 0) - (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", instruction); + (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode); #endif - /* Re-set OP list */ + h = lookup_hash(mcode, 1); + + if ((h == NULL) || (h->opcode == NULL)) return 0; + + if (h->size == 3) + { + iaddr = imem_addr ((uint32)PC + 2); + mcode = (mcode << 16) | get_longword( iaddr ); + } + + /* Re-set OP list. */ OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0; - /* for push/pop/pushrtn with RA instructions */ - if ((INST_HAS_REG_LIST) && (mcode & 0x800000)) - OP[2] = 1; /* Set 1 for RA operand */ - - get_operands (&instruction->operands, mcode, instruction->size); - - State.ins_type = instruction->flags; - //ins_type_counters[ (int)State.ins_type ]++; - sprintf(func,"OP_%X_%X",instruction->match,(32 - instruction->match_bits)); - /* Check for appropriate opcode function */ - for ( ;s->opcode!=0;s++) - { - if (strcmp(s->fname,func) == 0) - break; - } - (s->func)(); + /* for push/pop/pushrtn with RA instructions. */ + if ((h->format & REG_LIST) && (mcode & 0x800000)) + OP[2] = 1; /* Set 1 for RA operand. */ + + /* numops == 0 means, no operands. */ + if (((h->ops) != NULL) && (((h->ops)->numops) != 0)) + get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops); + + //State.ins_type = h->flags; + + (h->ops->func)(); + + return h->size; } static char * @@ -357,8 +436,8 @@ do { if (comma-- == 0) { - *--endbuf = ','; - comma = 2; + *--endbuf = ','; + comma = 2; } *--endbuf = (value % 10) + '0'; @@ -374,17 +453,17 @@ for (i = 0; i < IMEM_SEGMENTS; i++) { if (State.mem.insn[i]) - free (State.mem.insn[i]); + free (State.mem.insn[i]); } for (i = 0; i < DMEM_SEGMENTS; i++) { if (State.mem.data[i]) - free (State.mem.data[i]); + free (State.mem.data[i]); } for (i = 0; i < UMEM_SEGMENTS; i++) { if (State.mem.unif[i]) - free (State.mem.unif[i]); + free (State.mem.unif[i]); } /* Always allocate dmem segment 0. This contains the IMAP and DMAP registers. */ @@ -408,13 +487,13 @@ set_dmap_register (int reg_nr, unsigned long value) { uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA - + DMAP0_OFFSET + 2 * reg_nr); + + DMAP0_OFFSET + 2 * reg_nr); WRITE_16 (raw, value); #ifdef DEBUG if ((cr16_debug & DEBUG_MEMORY)) { (*cr16_callback->printf_filtered) - (cr16_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value); + (cr16_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value); } #endif } @@ -423,7 +502,7 @@ dmap_register (void *regcache, int reg_nr) { uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA - + DMAP0_OFFSET + 2 * reg_nr); + + DMAP0_OFFSET + 2 * reg_nr); return READ_16 (raw); } @@ -431,13 +510,13 @@ set_imap_register (int reg_nr, unsigned long value) { uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA - + IMAP0_OFFSET + 2 * reg_nr); + + IMAP0_OFFSET + 2 * reg_nr); WRITE_16 (raw, value); #ifdef DEBUG if ((cr16_debug & DEBUG_MEMORY)) { (*cr16_callback->printf_filtered) - (cr16_callback, "mem: imap%d=0x%04lx\n", reg_nr, value); + (cr16_callback, "mem: imap%d=0x%04lx\n", reg_nr, value); } #endif } @@ -446,7 +525,7 @@ imap_register (void *regcache, int reg_nr) { uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA - + IMAP0_OFFSET + 2 * reg_nr); + + IMAP0_OFFSET + 2 * reg_nr); return READ_16 (raw); } @@ -485,11 +564,11 @@ unsigned long sim_cr16_translate_dmap_addr (unsigned long offset, - int nr_bytes, - unsigned long *phys, - void *regcache, - unsigned long (*dmap_register) (void *regcache, - int reg_nr)) + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, + int reg_nr)) { short map; int regno; @@ -522,22 +601,22 @@ int sp = ((map & 0x3000) >> 12); int segno = (map & 0x3ff); switch (sp) - { - case 0: /* 00: Unified memory */ - *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset; - last_to = "unified"; - break; - case 1: /* 01: Instruction Memory */ - *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset; - last_to = "chip-insn"; - break; - case 2: /* 10: Internal data memory */ - *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset; - last_to = "chip-data"; - break; - case 3: /* 11: Reserved */ - return 0; - } + { + case 0: /* 00: Unified memory */ + *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset; + last_to = "unified"; + break; + case 1: /* 01: Instruction Memory */ + *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset; + last_to = "chip-insn"; + break; + case 2: /* 10: Internal data memory */ + *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset; + last_to = "chip-data"; + break; + case 3: /* 11: Reserved */ + return 0; + } } #endif return nr_bytes; @@ -548,11 +627,11 @@ unsigned long sim_cr16_translate_imap_addr (unsigned long offset, - int nr_bytes, - unsigned long *phys, - void *regcache, - unsigned long (*imap_register) (void *regcache, - int reg_nr)) + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*imap_register) (void *regcache, + int reg_nr)) { short map; int regno; @@ -591,8 +670,8 @@ offset = (offset % 0x800); *phys = SIM_CR16_MEMORY_INSN + offset; if (offset + nr_bytes > 0x800) - /* don't cross VM boundary */ - nr_bytes = 0x800 - offset; + /* don't cross VM boundary */ + nr_bytes = 0x800 - offset; last_to = "test-insn"; break; } @@ -600,14 +679,12 @@ } unsigned long -sim_cr16_translate_addr (unsigned long memaddr, - int nr_bytes, - unsigned long *targ_addr, - void *regcache, - unsigned long (*dmap_register) (void *regcache, - int reg_nr), - unsigned long (*imap_register) (void *regcache, - int reg_nr)) +sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes, + unsigned long *targ_addr, void *regcache, + unsigned long (*dmap_register) (void *regcache, + int reg_nr), + unsigned long (*imap_register) (void *regcache, + int reg_nr)) { unsigned long phys; unsigned long seg; @@ -625,59 +702,59 @@ if (old_segment_mapping) { switch (seg) - { - case 0x00: /* DMAP translated memory */ - seg = 0x10; - break; - case 0x01: /* IMAP translated memory */ - seg = 0x11; - break; - case 0x10: /* On-chip data memory */ - seg = 0x02; - break; - case 0x11: /* On-chip insn memory */ - seg = 0x01; - break; - case 0x12: /* Unified memory */ - seg = 0x00; - break; - } + { + case 0x00: /* DMAP translated memory */ + seg = 0x10; + break; + case 0x01: /* IMAP translated memory */ + seg = 0x11; + break; + case 0x10: /* On-chip data memory */ + seg = 0x02; + break; + case 0x11: /* On-chip insn memory */ + seg = 0x01; + break; + case 0x12: /* Unified memory */ + seg = 0x00; + break; + } } switch (seg) { - case 0x00: /* Physical unified memory */ + case 0x00: /* Physical unified memory */ last_from = "phys-unified"; last_to = "unified"; phys = SIM_CR16_MEMORY_UNIFIED + off; if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) - nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); + nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); break; - case 0x01: /* Physical instruction memory */ + case 0x01: /* Physical instruction memory */ last_from = "phys-insn"; last_to = "chip-insn"; phys = SIM_CR16_MEMORY_INSN + off; if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) - nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); + nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); break; - case 0x02: /* Physical data memory segment */ + case 0x02: /* Physical data memory segment */ last_from = "phys-data"; last_to = "chip-data"; phys = SIM_CR16_MEMORY_DATA + off; if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) - nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); + nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); break; - case 0x10: /* in logical data address segment */ + case 0x10: /* in logical data address segment */ nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache, - dmap_register); + dmap_register); break; - case 0x11: /* in logical instruction address segment */ + case 0x11: /* in logical instruction address segment */ nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache, - imap_register); + imap_register); break; default: @@ -705,35 +782,35 @@ case 0x00: /* Unified memory */ { - memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS]; - last_segname = "umem"; - break; + memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS]; + last_segname = "umem"; + break; } case 0x01: /* On-chip insn memory */ { - memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS]; - last_segname = "imem"; - break; + memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS]; + last_segname = "imem"; + break; } case 0x02: /* On-chip data memory */ { - if ((phys_addr & 0xff00) == 0xff00) - { - phys_addr = (phys_addr & 0xffff); - if (phys_addr == DMAP2_SHADDOW) - { - phys_addr = DMAP2_OFFSET; - last_segname = "dmap"; - } - else - last_segname = "reg"; - } - else - last_segname = "dmem"; - memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS]; - break; + if ((phys_addr & 0xff00) == 0xff00) + { + phys_addr = (phys_addr & 0xffff); + if (phys_addr == DMAP2_SHADDOW) + { + phys_addr = DMAP2_OFFSET; + last_segname = "dmap"; + } + else + last_segname = "reg"; + } + else + last_segname = "dmem"; + memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS]; + break; } default: @@ -746,10 +823,10 @@ { *memory = calloc (1, SEGMENT_SIZE); if (*memory == NULL) - { - (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n"); - return State.mem.fault; - } + { + (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n"); + return State.mem.fault; + } } offset = (phys_addr % SEGMENT_SIZE); @@ -766,15 +843,15 @@ static int xfer_mem (SIM_ADDR virt, - unsigned char *buffer, - int size, - int write_p) + unsigned char *buffer, + int size, + int write_p) { uint8 *memory; unsigned long phys; int phys_size; phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL, - dmap_register, imap_register); + dmap_register, imap_register); if (phys_size == 0) return 0; @@ -784,12 +861,12 @@ if ((cr16_debug & DEBUG_INSTRUCTION) != 0) { (*cr16_callback->printf_filtered) - (cr16_callback, - "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n", - (write_p ? "write" : "read"), - phys_size, virt, last_from, - phys, last_to, - (long) memory, last_segname); + (cr16_callback, + "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n", + (write_p ? "write" : "read"), + phys_size, virt, last_from, + phys, last_to, + (long) memory, last_segname); } #endif @@ -828,11 +905,11 @@ return xfer_mem( addr, buffer, size, 0); } - SIM_DESC sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv) { struct simops *s; + struct hash_entry *h; static int init_p = 0; char **p; @@ -848,18 +925,124 @@ for (p = argv + 1; *p; ++p) { if (strcmp (*p, "-oldseg") == 0) - old_segment_mapping = 1; + old_segment_mapping = 1; #ifdef DEBUG else if (strcmp (*p, "-t") == 0) - cr16_debug = DEBUG; + cr16_debug = DEBUG; else if (strncmp (*p, "-t", 2) == 0) - cr16_debug = atoi (*p + 2); + cr16_debug = atoi (*p + 2); #endif else - (*cr16_callback->printf_filtered) (cr16_callback, "ERROR: unsupported option(s): %s\n",*p); + (*cr16_callback->printf_filtered) (cr16_callback, "ERROR: unsupported option(s): %s\n",*p); } #endif + /* put all the opcodes in the hash table. */ + if (!init_p++) + { + for (s = Simops; s->func; s++) + { + switch(32 - s->mask) + { + case 0x4: + h = &hash_table[hash(s->opcode, 0)]; + break; + + case 0x7: + if (((s->opcode << 1) >> 4) != 0) + h = &hash_table[hash((s->opcode << 1) >> 4, 0)]; + else + h = &hash_table[hash((s->opcode << 1), 0)]; + break; + + case 0x8: + if ((s->opcode >> 4) != 0) + h = &hash_table[hash(s->opcode >> 4, 0)]; + else + h = &hash_table[hash(s->opcode, 0)]; + break; + + case 0x9: + if (((s->opcode >> 1) >> 4) != 0) + h = &hash_table[hash((s->opcode >>1) >> 4, 0)]; + else + h = &hash_table[hash((s->opcode >> 1), 0)]; + break; + + case 0xa: + if ((s->opcode >> 8) != 0) + h = &hash_table[hash(s->opcode >> 8, 0)]; + else if ((s->opcode >> 4) != 0) + h = &hash_table[hash(s->opcode >> 4, 0)]; + else + h = &hash_table[hash(s->opcode, 0)]; + break; + + case 0xc: + if ((s->opcode >> 8) != 0) + h = &hash_table[hash(s->opcode >> 8, 0)]; + else if ((s->opcode >> 4) != 0) + h = &hash_table[hash(s->opcode >> 4, 0)]; + else + h = &hash_table[hash(s->opcode, 0)]; + break; + + case 0xd: + if (((s->opcode >> 1) >> 8) != 0) + h = &hash_table[hash((s->opcode >>1) >> 8, 0)]; + else if (((s->opcode >> 1) >> 4) != 0) + h = &hash_table[hash((s->opcode >>1) >> 4, 0)]; + else + h = &hash_table[hash((s->opcode >>1), 0)]; + break; + + case 0x10: + if ((s->opcode >> 0xc) != 0) + h = &hash_table[hash(s->opcode >> 12, 0)]; + else if ((s->opcode >> 8) != 0) + h = &hash_table[hash(s->opcode >> 8, 0)]; + else if ((s->opcode >> 4) != 0) + h = &hash_table[hash(s->opcode >> 4, 0)]; + else + h = &hash_table[hash(s->opcode, 0)]; + break; + + case 0x14: + if ((s->opcode >> 16) != 0) + h = &hash_table[hash(s->opcode >> 16, 0)]; + else if ((s->opcode >> 12) != 0) + h = &hash_table[hash(s->opcode >> 12, 0)]; + else if ((s->opcode >> 8) != 0) + h = &hash_table[hash(s->opcode >> 8, 0)]; + else if ((s->opcode >> 4) != 0) + h = &hash_table[hash(s->opcode >> 4, 0)]; + else + h = &hash_table[hash(s->opcode, 0)]; + break; + default: + break; + } + + /* go to the last entry in the chain. */ + while (h->next) + h = h->next; + + if (h->ops) + { + h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); + if (!h->next) + perror ("malloc failure"); + + h = h->next; + } + h->ops = s; + h->mask = s->mask; + h->opcode = s->opcode; + h->format = s->format; + h->size = s->size; + } + } + /* reset the processor state */ if (!State.mem.data[0]) sim_size (1); @@ -907,7 +1090,7 @@ is uint16 this is modulo'ed onto 0x0e5d. */ phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL, - dmap_register); + dmap_register); if (phys_size == 0) { mem = State.mem.fault; @@ -918,11 +1101,11 @@ if ((cr16_debug & DEBUG_MEMORY)) { (*cr16_callback->printf_filtered) - (cr16_callback, - "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", - offset, last_from, - phys, phys_size, last_to, - (long) mem, last_segname); + (cr16_callback, + "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", + offset, last_from, + phys, phys_size, last_to, + (long) mem, last_segname); } #endif return mem; @@ -934,7 +1117,7 @@ unsigned long phys; uint8 *mem; int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL, - imap_register); + imap_register); if (phys_size == 0) { return State.mem.fault; @@ -944,11 +1127,11 @@ if ((cr16_debug & DEBUG_MEMORY)) { (*cr16_callback->printf_filtered) - (cr16_callback, - "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", - offset, last_from, - phys, phys_size, last_to, - (long) mem, last_segname); + (cr16_callback, + "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", + offset, last_from, + phys, phys_size, last_to, + (long) mem, last_segname); } #endif return mem; @@ -969,8 +1152,8 @@ void sim_resume (SIM_DESC sd, int step, int siggnal) { - uint32 mask = 0, ins_found = 0; - uint64 mcode=0; + uint32 curr_ins_size = 0; + uint64 mcode = 0; uint8 *iaddr; #ifdef DEBUG @@ -1009,94 +1192,42 @@ do { iaddr = imem_addr ((uint32)PC); - ins_found = 0; if (iaddr == State.mem.fault) - { - State.exception = SIGBUS; - break; - } + { + State.exception = SIGBUS; + break; + } mcode = get_longword( iaddr ); State.pc_changed = 0; - /* Start searching from end of instruction table. */ - const inst *instruction = &cr16_instruction[NUMOPCODES - 2]; - - /* Loop over instruction table until a full match is found. */ - while (instruction >= cr16_instruction) - { - mask = (((1 << (32 - instruction->match_bits)) -1) << - instruction->match_bits); - - /* Adjuest mask for branch with 2 word instructions. */ - if ((IS_INSN_MNEMONIC("b") && instruction->size == 2)) - mask = 0xff0f0000; - - if ((mcode & mask) == (BIN(instruction->match, instruction->match_bits))) - { - ins_found = 1; - break; - } - else - instruction--; - } + curr_ins_size = do_run(mcode); #if CR16_DEBUG (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode); #endif - if ((mcode == 0x0L) /*|| (!ins_found )*/) - { - State.exception = SIG_CR16_EXIT; /* exit trap */ - break; - } - /* Check if the ins_found is '0', then set illigel instruction trap */ - if ( !ins_found ) - State.exception = SIGILL; - else - { - /* For 3 word instructions only */ - if (instruction->size == 3) - { - iaddr = imem_addr ((uint32)PC + 2); - mcode = (mcode << 16) | get_longword( iaddr ); - } - - do_run(instruction, mcode); - } - - /* If the PC of the current instruction matches RPT_E then - schedule a branch to the loop start. If one of those - instructions happens to be a branch, than that instruction - will be ignored */ if (!State.pc_changed) - { - switch (instruction->size) - { - case 1: - SET_PC (PC + 2); /* For 1 word instructions */ - break; - case 2: - SET_PC (PC + 4); /* For 2 word instructions */ - break; - case 3: - SET_PC (PC + 6); /* For 3 word instructions */ - break; - default: break; - } + { + if (curr_ins_size == 0) + { + State.exception = SIG_CR16_EXIT; /* exit trap */ + break; + } + else + SET_PC (PC + (curr_ins_size * 2)); /* For word instructions. */ + } - } - - /* Check for a breakpoint trap on this instruction. This - overrides any pending branches or loops */ #if 0 + /* Check for a breakpoint trap on this instruction. This + overrides any pending branches or loops */ if (PSR_DB && PC == DBS) - { - SET_BPC (PC); - SET_BPSR (PSR); - SET_PC (SDBT_VECTOR_START); - } + { + SET_BPC (PC); + SET_BPSR (PSR); + SET_PC (SDBT_VECTOR_START); + } #endif /* Writeback all the DATA / PC changes */ @@ -1104,10 +1235,10 @@ #ifdef NEED_UI_LOOP_HOOK if (deprecated_ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) - { - ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; - deprecated_ui_loop_hook (0); - } + { + ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + deprecated_ui_loop_hook (0); + } #endif /* NEED_UI_LOOP_HOOK */ } while ( !State.exception && !stop_simulator); @@ -1133,99 +1264,99 @@ char buf4[40]; char buf5[40]; #if 0 - unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; - unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; - unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; - unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; - unsigned long left_total = left + left_parallel + left_cond + left_nops; - - unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; - unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; - unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; - unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; - unsigned long right_total = right + right_parallel + right_cond + right_nops; - - unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; - unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; - unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; - unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; - unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; - unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; - unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; - unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; - unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; - unsigned long total = (unknown + left_total + right_total + ins_long); - - int size = strlen (add_commas (buf1, sizeof (buf1), total)); - int parallel_size = strlen (add_commas (buf1, sizeof (buf1), - (left_parallel > right_parallel) ? left_parallel : right_parallel)); - int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); - int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); - int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); + unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; + unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; + unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; + unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; + unsigned long left_total = left + left_parallel + left_cond + left_nops; + + unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; + unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; + unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; + unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; + unsigned long right_total = right + right_parallel + right_cond + right_nops; + + unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; + unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; + unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; + unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; + unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; + unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; + unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; + unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; + unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; + unsigned long total = (unknown + left_total + right_total + ins_long); + + int size = strlen (add_commas (buf1, sizeof (buf1), total)); + int parallel_size = strlen (add_commas (buf1, sizeof (buf1), + (left_parallel > right_parallel) ? left_parallel : right_parallel)); + int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); + int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); + int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", - size, add_commas (buf1, sizeof (buf1), left_total), - normal_size, add_commas (buf2, sizeof (buf2), left), - parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), - cond_size, add_commas (buf4, sizeof (buf4), left_cond), - nop_size, add_commas (buf5, sizeof (buf5), left_nops)); + "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", + size, add_commas (buf1, sizeof (buf1), left_total), + normal_size, add_commas (buf2, sizeof (buf2), left), + parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), + cond_size, add_commas (buf4, sizeof (buf4), left_cond), + nop_size, add_commas (buf5, sizeof (buf5), left_nops)); (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", - size, add_commas (buf1, sizeof (buf1), right_total), - normal_size, add_commas (buf2, sizeof (buf2), right), - parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), - cond_size, add_commas (buf4, sizeof (buf4), right_cond), - nop_size, add_commas (buf5, sizeof (buf5), right_nops)); + "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", + size, add_commas (buf1, sizeof (buf1), right_total), + normal_size, add_commas (buf2, sizeof (buf2), right), + parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), + cond_size, add_commas (buf4, sizeof (buf4), right_cond), + nop_size, add_commas (buf5, sizeof (buf5), right_nops)); if (ins_long) (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s long instruction(s)\n", - size, add_commas (buf1, sizeof (buf1), ins_long)); + "executed %*s long instruction(s)\n", + size, add_commas (buf1, sizeof (buf1), ins_long)); if (parallel) (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s parallel instruction(s)\n", - size, add_commas (buf1, sizeof (buf1), parallel)); + "executed %*s parallel instruction(s)\n", + size, add_commas (buf1, sizeof (buf1), parallel)); if (leftright) (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s instruction(s) encoded L->R\n", - size, add_commas (buf1, sizeof (buf1), leftright)); + "executed %*s instruction(s) encoded L->R\n", + size, add_commas (buf1, sizeof (buf1), leftright)); if (rightleft) (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s instruction(s) encoded R->L\n", - size, add_commas (buf1, sizeof (buf1), rightleft)); + "executed %*s instruction(s) encoded R->L\n", + size, add_commas (buf1, sizeof (buf1), rightleft)); if (unknown) (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s unknown instruction(s)\n", - size, add_commas (buf1, sizeof (buf1), unknown)); + "executed %*s unknown instruction(s)\n", + size, add_commas (buf1, sizeof (buf1), unknown)); if (cond_true) (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s instruction(s) due to EXExxx condition being true\n", - size, add_commas (buf1, sizeof (buf1), cond_true)); + "executed %*s instruction(s) due to EXExxx condition being true\n", + size, add_commas (buf1, sizeof (buf1), cond_true)); if (cond_false) (*cr16_callback->printf_filtered) (cr16_callback, - "skipped %*s instruction(s) due to EXExxx condition being false\n", - size, add_commas (buf1, sizeof (buf1), cond_false)); + "skipped %*s instruction(s) due to EXExxx condition being false\n", + size, add_commas (buf1, sizeof (buf1), cond_false)); if (cond_jump) (*cr16_callback->printf_filtered) (cr16_callback, - "skipped %*s instruction(s) due to conditional branch succeeding\n", - size, add_commas (buf1, sizeof (buf1), cond_jump)); + "skipped %*s instruction(s) due to conditional branch succeeding\n", + size, add_commas (buf1, sizeof (buf1), cond_jump)); (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s cycle(s)\n", - size, add_commas (buf1, sizeof (buf1), cycles)); + "executed %*s cycle(s)\n", + size, add_commas (buf1, sizeof (buf1), cycles)); (*cr16_callback->printf_filtered) (cr16_callback, - "executed %*s total instructions\n", - size, add_commas (buf1, sizeof (buf1), total)); + "executed %*s total instructions\n", + size, add_commas (buf1, sizeof (buf1), total)); #endif } @@ -1278,12 +1409,12 @@ switch (State.exception) { - case SIG_CR16_STOP: /* stop instruction */ + case SIG_CR16_STOP: /* stop instruction */ *reason = sim_stopped; *sigrc = 0; break; - case SIG_CR16_EXIT: /* exit trap */ + case SIG_CR16_EXIT: /* exit trap */ *reason = sim_exited; *sigrc = GPR (2); break; @@ -1298,12 +1429,12 @@ // *sigrc = TARGET_SIGNAL_IAD; // break; - default: /* some signal */ + default: /* some signal */ *reason = sim_stopped; if (stop_simulator && !State.exception) - *sigrc = TARGET_SIGNAL_INT; + *sigrc = TARGET_SIGNAL_INT; else - *sigrc = State.exception; + *sigrc = State.exception; break; } @@ -1439,8 +1570,8 @@ prog_bfd_was_opened_p = 0; } prog_bfd = sim_load_file (sd, myname, cr16_callback, prog, abfd, - sim_kind == SIM_OPEN_DEBUG, - 1/*LMA*/, sim_write); + sim_kind == SIM_OPEN_DEBUG, + 1/*LMA*/, sim_write); if (prog_bfd == NULL) return SIM_RC_FAIL; prog_bfd_was_opened_p = abfd == NULL; Index: simops.c =================================================================== RCS file: /cvs/src/src/sim/cr16/simops.c,v retrieving revision 1.1 diff -c -u -a -r1.1 simops.c --- simops.c 8 Apr 2008 09:20:06 -0000 1.1 +++ simops.c 2 May 2008 11:07:37 -0000 @@ -14,8 +14,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License along - with this program. If not, see <http://www.gnu.org/licenses/>. */ + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "config.h" @@ -40,100 +40,58 @@ enum op_types { OP_VOID, OP_CONSTANT3, - OP_CONSTANT3_OUTPUT, OP_UCONSTANT3, - OP_UCONSTANT3_OUTPUT, - OP_UCONSTANT3_1, - OP_UCONSTANT3_1_OUTPUT, OP_CONSTANT4, - OP_CONSTANT4_OUTPUT, OP_CONSTANT4_1, - OP_CONSTANT4_1_OUTPUT, OP_CONSTANT5, - OP_CONSTANT5_OUTPUT, OP_CONSTANT6, - OP_CONSTANT6_OUTPUT, OP_CONSTANT16, - OP_CONSTANT16_OUTPUT, OP_UCONSTANT16, - OP_UCONSTANT16_OUTPUT, OP_CONSTANT20, - OP_CONSTANT20_OUTPUT, OP_UCONSTANT20, - OP_UCONSTANT20_OUTPUT, OP_CONSTANT32, - OP_UCONSTANT32_OUTPUT, OP_UCONSTANT32, - OP_CONSTANT32_OUTPUT, OP_MEMREF, OP_MEMREF2, OP_MEMREF3, OP_DISP5, - OP_DISP5_OUTPUT, OP_DISP17, - OP_DISP17_OUTPUT, OP_DISP25, - OP_DISP25_OUTPUT, OP_DISPE9, - OP_DISPE9_OUTPUT, //OP_ABS20, OP_ABS20_OUTPUT, //OP_ABS24, OP_ABS24_OUTPUT, OP_R_BASE_DISPS16, - OP_R_BASE_DISPS16_OUTPUT, OP_R_BASE_DISP20, - OP_R_BASE_DISP20_OUTPUT, OP_R_BASE_DISPS20, - OP_R_BASE_DISPS20_OUTPUT, OP_R_BASE_DISPE20, - OP_R_BASE_DISPE20_OUTPUT, OP_RP_BASE_DISPE0, - OP_RP_BASE_DISPE0_OUTPUT, OP_RP_BASE_DISP4, - OP_RP_BASE_DISP4_OUTPUT, OP_RP_BASE_DISPE4, - OP_RP_BASE_DISPE4_OUTPUT, OP_RP_BASE_DISP14, - OP_RP_BASE_DISP14_OUTPUT, OP_RP_BASE_DISP16, - OP_RP_BASE_DISP16_OUTPUT, OP_RP_BASE_DISP20, - OP_RP_BASE_DISP20_OUTPUT, OP_RP_BASE_DISPS20, - OP_RP_BASE_DISPS20_OUTPUT, OP_RP_BASE_DISPE20, - OP_RP_BASE_DISPE20_OUTPUT, OP_R_INDEX7_ABS20, - OP_R_INDEX7_ABS20_OUTPUT, OP_R_INDEX8_ABS20, - OP_R_INDEX8_ABS20_OUTPUT, OP_RP_INDEX_DISP0, - OP_RP_INDEX_DISP0_OUTPUT, OP_RP_INDEX_DISP14, - OP_RP_INDEX_DISP14_OUTPUT, OP_RP_INDEX_DISP20, - OP_RP_INDEX_DISP20_OUTPUT, OP_RP_INDEX_DISPS20, - OP_RP_INDEX_DISPS20_OUTPUT, OP_REG, - OP_REG_OUTPUT, OP_REGP, - OP_REGP_OUTPUT, OP_PROC_REG, - OP_PROC_REG_OUTPUT, OP_PROC_REGP, - OP_PROC_REGP_OUTPUT, OP_COND, - OP_COND_OUTPUT, - OP_RA, - OP_RA_OUTPUT + OP_RA }; @@ -226,6 +184,7 @@ /* only issue an update if the register is being changed. */ if ((State.cregs[cr] & ~mask) != val) SLOT_PEND_MASK (State.cregs[cr], mask, val); + return val; } @@ -358,16 +317,13 @@ break; case OP_REG: - case OP_REG_OUTPUT: case OP_REGP: - case OP_REGP_OUTPUT: sprintf (p, "%sr%d", comma, OP[i]); p += strlen (p); comma = ","; break; case OP_PROC_REG: - case OP_PROC_REG_OUTPUT: sprintf (p, "%scr%d", comma, OP[i]); p += strlen (p); comma = ","; @@ -432,12 +388,6 @@ (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, ""); break; - case OP_REG_OUTPUT: - case OP_REGP_OUTPUT: - case OP_PROC_REG_OUTPUT: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, "---"); - break; - case OP_REG: (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) GPR (OP[i])); @@ -2444,11 +2394,10 @@ OP_6_8 () { uint16 a = OP[0]; - uint32 addr = (GPR (OP[1])), tmp; + uint16 b = (GPR (OP[1])); trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID); - tmp = RW (addr); - SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + SET_PSR_F (b & (1 << a)); + trace_output_16 (b); } /* tbit. */ @@ -2456,11 +2405,10 @@ OP_7_8 () { uint16 a = GPR (OP[0]); - uint32 addr = (GPR (OP[1])), tmp; + uint16 b = (GPR (OP[1])); trace_input ("tbit", OP_REG, OP_REG, OP_VOID); - tmp = RW (addr); - SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + SET_PSR_F (b & (1 << a)); + trace_output_16 (b); } @@ -4368,8 +4316,8 @@ void OP_62_8 () { - int32 tmp, b = (GPR32 (OP[1])); - int16 a = (GPR (OP[0])); + int32 tmp; + int16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID); tmp = a * b; SET_GPR32 (OP[1], tmp); @@ -4380,8 +4328,8 @@ void OP_63_8 () { - uint32 tmp, b = (GPR32 (OP[1])); - uint16 a = (GPR (OP[0])); + uint32 tmp; + uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("muluw", OP_REG, OP_REGP, OP_VOID); tmp = a * b; SET_GPR32 (OP[1], tmp);Index: ChangeLog =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ChangeLog,v retrieving revision 1.2 diff -c -u -r1.2 ChangeLog --- ChangeLog 8 Apr 2008 12:45:37 -0000 1.2 +++ ChangeLog 2 May 2008 10:53:24 -0000 @@ -1,3 +1,17 @@ +2008-05-02 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * cbitb.cgs, cbitw.cgs, sbitb.cgs, sbitw.cgs, tbit.cgs, tbitb.cgs, + tbitw.cgs, hw-trap.ms, uread16.ms, uread32.ms: New testcases. + addb.cgs, addd.cgs, addi.cgs, andb.cgs, andd.cgs, andw.cgs, ashub.cgs, + ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, cmpi.cgs, + cmpw.cgs, jlt.cgs, jump.cgs, loadd.cgs, loadw.cgs, lshb.cgs, lshb_i.cgs, + lshd.cgs, lshd_i.cgs, lshw.cgs, lshw_i.cgs, movb.cgs, movd.cgs, + movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, movzw.cgs, mulb.cgs, + muluw.cgs, mulw.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, + pop3.cgs, popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, + push3.cgs: Update testcase comment. + bnc8.cgs, bnc24.cgs and ret.cgs: Removed. + 2008-04-08 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * allinsn.exp: Remove target_alias and global_ld_options. Index: addb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/addb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 addb.cgs --- addb.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ addb.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for addb $dr,$sr +# cr16 testcase for addb $sr, reg # mach(): cr16 .include "testutils.inc" Index: addd.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/addd.cgs,v retrieving revision 1.1 diff -c -u -r1.1 addd.cgs --- addd.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ addd.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for addd $sr,$dr +# cr16 testcase for addd $sr, regp # mach(): cr16 .include "testutils.inc" Index: addi.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/addi.cgs,v retrieving revision 1.1 diff -c -u -r1.1 addi.cgs --- addi.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ addi.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for addi #$simm8, $dr +# cr16 testcase for addi $imm8, $dr # mach(): cr16 .include "testutils.inc" Index: andb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/andb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 andb.cgs --- andb.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ andb.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for and $dr,$sr +# cr16 testcase for and $sr,$dr # mach(): cr16 .include "testutils.inc" Index: andd.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/andd.cgs,v retrieving revision 1.1 diff -c -u -r1.1 andd.cgs --- andd.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ andd.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for and $dr,$sr +# cr16 testcase for and $sr,$dr # mach(): cr16 .include "testutils.inc" Index: andw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/andw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 andw.cgs --- andw.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ andw.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for and $dr,$sr +# cr16 testcase for and $sr,$dr # mach(): cr16 .include "testutils.inc" Index: ashub.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ashub.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ashub.cgs --- ashub.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ ashub.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ashub $dr,$sr +# cr16 testcase for ashub $sr,$dr # mach(): cr16 .include "testutils.inc" Index: ashub_i.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ashub_i.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ashub_i.cgs --- ashub_i.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ ashub_i.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ashub $dr,$sr +# cr16 testcase for ashub $sr,$dr # mach(): cr16 .include "testutils.inc" Index: ashud.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ashud.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ashud.cgs --- ashud.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ ashud.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ashud $dr,$sr +# cr16 testcase for ashud $sr,$dr # mach(): cr16 .include "testutils.inc" Index: ashud_i.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ashud_i.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ashud_i.cgs --- ashud_i.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ ashud_i.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ashud $dr,$sr +# cr16 testcase for ashud $sr,$dr # mach(): cr16 .include "testutils.inc" Index: ashuw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ashuw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ashuw.cgs --- ashuw.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ ashuw.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ashuw $dr,$sr +# cr16 testcase for ashuw $sr,$dr # mach(): cr16 .include "testutils.inc" Index: ashuw_i.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ashuw_i.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ashuw_i.cgs --- ashuw_i.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ ashuw_i.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ashuw $dr,$sr +# cr16 testcase for ashuw $sr,$dr # mach(): cr16 .include "testutils.inc" Index: cmpi.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/cmpi.cgs,v retrieving revision 1.1 diff -c -u -r1.1 cmpi.cgs --- cmpi.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ cmpi.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for cmpi $src2,#$simm16 +# cr16 testcase for cmpi $imm16, reg # mach(): cr16 .include "testutils.inc" Index: cmpw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/cmpw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 cmpw.cgs --- cmpw.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ cmpw.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for cmp $src1,$src2 +# cr16 testcase for cmp $imm, reg # mach(): cr16 .include "testutils.inc" Index: jlt.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/jlt.cgs,v retrieving revision 1.1 diff -c -u -r1.1 jlt.cgs --- jlt.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ jlt.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for jlt (repl) +# cr16 testcase for jlt (regp) # mach(): cr16 .include "testutils.inc" Index: jump.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/jump.cgs,v retrieving revision 1.1 diff -c -u -r1.1 jump.cgs --- jump.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ jump.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for jmp $sr +# cr16 testcase for jmp (regp) # mach(): cr16 .include "testutils.inc" Index: loadd.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/loadd.cgs,v retrieving revision 1.1 diff -c -u -r1.1 loadd.cgs --- loadd.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ loadd.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ldb $dr,@$sr +# cr16 testcase for loadd 0(regp),regp # mach(): cr16 .include "testutils.inc" Index: loadw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/loadw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 loadw.cgs --- loadw.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ loadw.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for ldb $dr,@$sr +# cr16 testcase for loadw 0(regp), (regp) # mach(): cr16 .include "testutils.inc" Index: lshb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/lshb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 lshb.cgs --- lshb.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ lshb.cgs 2 May 2008 10:53:24 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for sll $dr,$sr +# cr16 testcase for lshb count, reg # mach(): cr16 .include "testutils.inc" start - .global sll -sll: + .global lshb +lshb: movb $6, r4 movb $1, r5 lshb r5, r4 Index: lshb_i.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/lshb_i.cgs,v retrieving revision 1.1 diff -c -u -r1.1 lshb_i.cgs --- lshb_i.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ lshb_i.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for lshb_i $dr,#$uimm5 +# cr16 testcase for lshb_i $uimm5, reg # mach(): cr16 .include "testutils.inc" Index: lshd.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/lshd.cgs,v retrieving revision 1.1 diff -c -u -r1.1 lshd.cgs --- lshd.cgs 8 Apr 2008 09:07:01 -0000 1.1 +++ lshd.cgs 2 May 2008 10:53:24 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for sll $dr,$sr +# cr16 testcase for lshd reg, regp # mach(): cr16 .include "testutils.inc" start - .global sll -sll: + .global lshd +lshd: movd $0x12345678, (r4,r3) movw $0x10, r5 lshd r5, (r4,r3) Index: lshd_i.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/lshd_i.cgs,v retrieving revision 1.1 diff -c -u -r1.1 lshd_i.cgs --- lshd_i.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ lshd_i.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for lshb_i $dr,#$uimm5 +# cr16 testcase for lshb_i $uimm5, regp # mach(): cr16 .include "testutils.inc" Index: lshw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/lshw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 lshw.cgs --- lshw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ lshw.cgs 2 May 2008 10:53:24 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for sll $dr,$sr +# cr16 testcase for lshw reg, reg # mach(): cr16 .include "testutils.inc" start - .global sll -sll: + .global lshw +lshw: movw $0x1234, r4 movw $8, r5 lshw r5, r4 Index: lshw_i.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/lshw_i.cgs,v retrieving revision 1.1 diff -c -u -r1.1 lshw_i.cgs --- lshw_i.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ lshw_i.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for lshb_i $dr,#$uimm5 +# cr16 testcase for lshb_i $uimm4, reg # mach(): cr16 .include "testutils.inc" Index: movb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movb.cgs --- movb.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movb.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for movb $sr,$dr +# cr16 testcase for movb $imm, reg # mach(): cr16 .include "testutils.inc" Index: movd.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movd.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movd.cgs --- movd.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movd.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for movd $sr,$dr +# cr16 testcase for movd $imm32, regp # mach(): cr16 .include "testutils.inc" Index: movw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movw.cgs --- movw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movw.cgs 2 May 2008 10:53:24 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for movw $sr,$dr +# cr16 testcase for movw $imm16, reg # mach(): cr16 .include "testutils.inc" Index: movxb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movxb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movxb.cgs --- movxb.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movxb.cgs 2 May 2008 10:53:25 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for movb $sr,$dr +# cr16 testcase for movb $imm4, reg # mach(): cr16 .include "testutils.inc" Index: movxw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movxw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movxw.cgs --- movxw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movxw.cgs 2 May 2008 10:53:25 -0000 @@ -1,4 +1,4 @@ -# cr16 testcase for movw $sr,$dr +# cr16 testcase for movw reg, regp # mach(): cr16 .include "testutils.inc" Index: movzb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movzb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movzb.cgs --- movzb.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movzb.cgs 2 May 2008 10:53:25 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for movb $sr,$dr +# cr16 testcase for movzb reg, reg # mach(): cr16 .include "testutils.inc" start - .global movb -movb: + .global movzb +movzb: movw $0x120f, r4 movw $0x1200, r5 Index: movzw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/movzw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 movzw.cgs --- movzw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ movzw.cgs 2 May 2008 10:53:25 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for movw $sr,$dr +# cr16 testcase for movzw reg, regp # mach(): cr16 .include "testutils.inc" start - .global movw -movw: + .global movzw +movzw: movb $0xff, r4 movd $0x12345678,(r6, r5) Index: mulb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/mulb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 mulb.cgs --- mulb.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ mulb.cgs 2 May 2008 10:53:25 -0000 @@ -7,11 +7,11 @@ .global mulb mulb: - movw $0x2303,r4 - movw $0x1207,r5 + movw $0x1234,r4 + movw $0x4567,r5 mulb r4, r5 - cmpb $21, r5 + cmpb $0xec, r5 beq ok1 not_ok: fail Index: muluw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/muluw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 muluw.cgs --- muluw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ muluw.cgs 2 May 2008 10:53:25 -0000 @@ -1,16 +1,16 @@ -# cr16 testcase for mul $dr,$sr +# cr16 testcase for muluw reg, regp # mach(): cr16 .include "testutils.inc" start - .global mul -mul: + .global muluw +muluw: movw $0xfff,r4 # fix for 0xffff movd $0xffffffff,(r6,r5) muluw r4, (r6,r5) - test_h_grp "(r6,r5)", 0xfffff001 + test_h_grp "(r6,r5)", 0xffef001 pass Index: mulw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/mulw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 mulw.cgs --- mulw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ mulw.cgs 2 May 2008 10:53:25 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for mul $dr,$sr +# cr16 testcase for mulw reg reg # mach(): cr16 .include "testutils.inc" start - .global mul -mul: + .global mulw +mulw: movw $0x1234,r4 movw $0x1234,r5 Index: orb.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/orb.cgs,v retrieving revision 1.1 diff -c -u -r1.1 orb.cgs --- orb.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ orb.cgs 2 May 2008 10:53:25 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for or $sr,$dr +# cr16 testcase for orb $imm, reg # mach(): cr16 .include "testutils.inc" start - .global or -or: + .global orb +orb: movb $3, r4 movb $6, r5 Index: ord.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/ord.cgs,v retrieving revision 1.1 diff -c -u -r1.1 ord.cgs --- ord.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ ord.cgs 2 May 2008 10:53:25 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for or $dr,$sr +# cr16 testcase for ord $imm32, regp # mach(): cr16 .include "testutils.inc" start - .global or -or: + .global ord +ord: movd $0x33333333, (r4,r3) movd $0x66666666, (r6,r5) Index: orw.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/orw.cgs,v retrieving revision 1.1 diff -c -u -r1.1 orw.cgs --- orw.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ orw.cgs 2 May 2008 10:53:25 -0000 @@ -1,12 +1,12 @@ -# cr16 testcase for or $dr,$sr +# cr16 testcase for orw reg, reg # mach(): cr16 .include "testutils.inc" start - .global or -or: + .global orw +orw: movw $3, r4 movw $6, r5 Index: pop1.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/pop1.cgs,v retrieving revision 1.1 diff -c -u -r1.1 pop1.cgs --- pop1.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ pop1.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global pop1 pop1: movd $0x1000, (sp) movw $0x2f50, r3 Index: pop2.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/pop2.cgs,v retrieving revision 1.1 diff -c -u -r1.1 pop2.cgs --- pop2.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ pop2.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global pop2 pop2: movd $0x1000, (sp) movw $0x2f50, r3 Index: pop3.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/pop3.cgs,v retrieving revision 1.1 diff -c -u -r1.1 pop3.cgs --- pop3.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ pop3.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global pop3 pop3: movd $0x1006, (sp) movd $0xabcd, (r3,r2) Index: popret1.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/popret1.cgs,v retrieving revision 1.1 diff -c -u -r1.1 popret1.cgs --- popret1.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ popret1.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global popret1 popret1: movd $0x1000, (sp) movw $0x2f50, r3 Index: popret2.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/popret2.cgs,v retrieving revision 1.1 diff -c -u -r1.1 popret2.cgs --- popret2.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ popret2.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global popret2 popret2: movd $0x1000, (sp) movw $0x2f50, r3 Index: popret3.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/popret3.cgs,v retrieving revision 1.1 diff -c -u -r1.1 popret3.cgs --- popret3.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ popret3.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global popret3 popret3: movd $0x1006, (sp) movd $ok, (ra) Index: push1.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/push1.cgs,v retrieving revision 1.1 diff -c -u -r1.1 push1.cgs --- push1.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ push1.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global push1 push1: movd $0x100a, (sp) movd $0xabcd, (ra) Index: push2.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/push2.cgs,v retrieving revision 1.1 diff -c -u -r1.1 push2.cgs --- push2.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ push2.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global push2 push2: movd $0x1006, (sp) movw $0x2f50, r5 Index: push3.cgs =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cr16/push3.cgs,v retrieving revision 1.1 diff -c -u -r1.1 push3.cgs --- push3.cgs 8 Apr 2008 09:07:02 -0000 1.1 +++ push3.cgs 2 May 2008 10:53:25 -0000 @@ -4,6 +4,8 @@ .include "testutils.inc" start + + .global push1 push1: movd $0x1006, (sp) movd $0xabcd, (ra)Attachment: cr16-sim-test-newfiles.tar.bz2
Description: Binary data
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