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Re: [rfc][3/3] gdbserver bi-arch support: fix s390x partial register access


On Mon, Jan 21, 2008 at 06:46:26PM +0100, Ulrich Weigand wrote:
> The second problem is that when *setting* a partial register value, current
> code always pads the remainder of the register with zero.  This is a problem
> with the PSW mask register on s390x, where one of the bits in the second
> half needs to be and remain set; otherwise the PSW is invalid and the
> inferior crashes.
> 
> The patch fixes this by changing usr_store_inferior_registers by using a
> read-modify-write cycle when partially updating a register so that the
> bits in the part of the register that is not changed keep their old
> values.

What do you think about passing data to the low target in this case?
For MIPS the right bits will be value-dependent - registers must be
sign extended.

-- 
Daniel Jacobowitz
CodeSourcery


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