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Re: [patch] Fix disarmed hw watchpoints after inferior's fork()
- From: Jan Kratochvil <jan dot kratochvil at redhat dot com>
- To: gdb-patches at sourceware dot org
- Cc: Daniel Jacobowitz <drow at false dot org>
- Date: Sat, 24 Nov 2007 17:02:01 +0100
- Subject: Re: [patch] Fix disarmed hw watchpoints after inferior's fork()
- References: <20071014155530.GA10094@host0.dyn.jankratochvil.net> <20071024192937.GC10943@caradoc.them.org>
On Wed, 24 Oct 2007 21:29:37 +0200, Daniel Jacobowitz wrote:
> On Sun, Oct 14, 2007 at 05:55:30PM +0200, Jan Kratochvil wrote:
> > Hi,
> >
> > currently on x86_64:
> > watch var
> > run
> > (inferior fork()s a forgotten child)
> > (inferior var++) - but it is not noticed by GDB!
> >
> > i386-nat.c keeps a single mirror of the hardware debug registers but these are
> > specific for each LWP and i386-nat.c is also called for multiple INFERIOR_PTIDs
> > - such as for the child PID during DETACH_BREAKPOINTS.
>
> You've added a per-process cache of the debug registers. I don't
> think we need one; instead we just need to find something halfway
> sensible to do when told to remove watchpoints from the child. The
> detach_breakpoints / reattach_breakpoints interface is a very ugly
> one and this is one of the reasons why.
While awareness of multiple threads/processes is not required for the
functionality it is at least required for sanity checking. Currently
the target uses just this interface to the lower layer:
#define I386_DR_LOW_SET_CONTROL(control) \
#define I386_DR_LOW_SET_ADDR(regnum, addr) \
#define I386_DR_LOW_RESET_ADDR(regnum) \
#define I386_DR_LOW_GET_STATUS() \
while the target threads/processes change underneath and it still tries to
cache it.
There are two ways for the fix:
(a) Make the CPU target multi-thread aware.
(b) (1) Implement multi-threading sanity checking into the CPU target.
(2) Fix the upper code violating the multi-threading sanity checks.
I chose (a) as it was simpler. You are suggesting (b)(2).
...
> I believe all Linux targets need the same sort of fix, since they all
> have some degree of cache now.
You are right my patch misses the non-x86 targets.
Regards,
Jan