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Re: AM33/2.0 support for mn10300-elf


On Aug  2, 2003, Andrew Cagney <ac131313@redhat.com> wrote:

> For the simulator, two refinements:

> +void fpu_disabled_exception     PARAMS ((SIM_DESC, sim_cpu *,
> address_word));
> The code needs to use strict ISO C.  It might be easier to just
> convert everything.

> +  store_word (addr + 4, data.high);
> +}
>   #endif  /* not WITH_COMMON */

> The MN10300 switched to sim/common long ago, the #if !WITH_COMMON code
> should be deleted.

> they can both be considered pretty "obvious".

> Other than that, its approved.

Having fixed the two items above, I'm going ahead and checking this
in.

Index: sim/mn10300/ChangeLog
from  Alexandre Oliva  <aoliva@redhat.com>
	2000-08-07  Graham Stott  <grahams@cygnus.co.uk>
	* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo.
	2000-05-29  Alexandre Oliva  <aoliva@cygnus.com>
	* interp.c (fpu_disabled_exception, fpu_unimp_exception,
	fpu_check_signal_exception): Take additional state arguments.
	Print exception type and call program_interrupt.  Adjust callers.
	(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
	fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional
	arguments.
	* mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception,
	fpu_check_signal_exception): Adjust prototypes.
	(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
	fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise.
	* am33-2.igen: Adjust calls.
	2000-05-19  Alexandre Oliva  <aoliva@cygnus.com>
	* op_utils.c (cmp2fcc): Moved...
	* interp.c: ... here.
	2000-05-18  Alexandre Oliva  <aoliva@cygnus.com>
	* am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or
	`signed64' where type width is relevant.
	2000-05-15  Alexandre Oliva  <aoliva@cygnus.com>
	* mn10300_sim.h: Include sim-fpu.h.
	(FD2FPU, FPU2FD): Enclose the FD argument in parentheses.
	(fpu_check_signal_exception): Declare.
	(struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise.
	(FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec.
	(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
	fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare.
	* interp.c (fpu_disabled_exception): Document.
	(fpu_unimp_exception): Likewise.
	(fpu_check_signal_exception): Define.
	(reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise.
	(reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise.
	(REG2VAL, ROUND, VAL2REG): Define shorthands.
	(fpu_status_ok): Define.
	(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
	fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define.
	* am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv,
	fmadd, fmsub, fnmadd, fnmsub): Use new functions.
	2000-04-27  Alexandre Oliva  <aoliva@cygnus.com>
	* interp.c (sim_create_inferior): Set PSW bit to enable FP insns
	if architecture is AM33/2.0.
	* am33.igen: Include am33-2.igen.
	2000-04-23  Alexandre Oliva  <aoliva@cygnus.com>
	* mn10300.igen (movm, call, ret, retf): Check for am33_2 too.
	* am33.igen (movm): Likewise.
	2000-04-19  Alexandre Oliva  <aoliva@cygnus.com>
	* am33.igen: Added `*am33_2' to some instructions that were
	missing it.
	2000-04-07  Alexandre Oliva  <aoliva@cygnus.com>
	* am33-2.igen: New file.  All insns implemented, but FP flags are
	only set for fcmp, exceptional conditions are not handled yet.
	* Makefile.in (IGEN_INSN): Added am33-2.igen.
	(tmp-igen): Added -M am33_2.
	* mn10300.igen, am33.igen: Added `*am33_2' to all insns.
	* gencode.c: Support FMT_D3.
	* mn10300_sim.h (dword): New type.
	(struct _state): Added fpregs.
	(REG_FPCR, FPCR): New define.  All assorted bitmaps.
	(XS2FS, AS2FS, Xf2FD): New macros.
	(FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise.
	(load_dword, store_dword): New functions or macros.
	(u642dw, dw2u64): New functions.
	(fpu_disabled_exception, fpu_unimp_exception): Declared.
	* interp.c (fpu_disabled_exception): Defined; no actual
	implementation.
	(fpu_unimp_exception): Likewise.
	* op_utils.c (cmp2fcc): New function.

Index: sim/mn10300/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mn10300/Makefile.in,v
retrieving revision 1.8
diff -u -p -r1.8 Makefile.in
--- sim/mn10300/Makefile.in 26 Jun 2004 21:44:56 -0000 1.8
+++ sim/mn10300/Makefile.in 26 Jun 2004 22:15:58 -0000
@@ -79,7 +79,7 @@ clean-igen:
 	cd ../igen && $(MAKE)
 
 IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
-IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen
+IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen $(srcdir)/am33-2.igen
 IGEN_DC=$(srcdir)/mn10300.dc
 tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
 	cd ../igen && $(MAKE)
@@ -87,6 +87,7 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../ige
 		$(IGEN_TRACE) \
 		-G gen-direct-access \
                 -M mn10300,am33 -G gen-multi-sim=am33 \
+		-M am33_2 \
 		-I $(srcdir) \
 		-i $(IGEN_INSN) \
 		-o $(IGEN_DC) \
Index: sim/mn10300/am33-2.igen
===================================================================
RCS file: sim/mn10300/am33-2.igen
diff -N sim/mn10300/am33-2.igen
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ sim/mn10300/am33-2.igen 26 Jun 2004 22:15:59 -0000
@@ -0,0 +1,2285 @@
+// data cache pre-fetch:
+
+// 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
+8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
+"dcpf"
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+
+  srcreg = translate_rreg (SD_, RN2);
+  load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 1010 0111 0000 0000; dcpf (sp)
+8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
+"dcpf"
+*am33_2
+{
+  PC = cia;
+
+  load_word (SP);
+}
+
+// 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
+8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
+"dcpf"
+*am33_2
+{
+  int srci, srcm;
+
+  PC = cia;
+
+  srci = translate_rreg (SD_, RN2);
+  srcm = translate_rreg (SD_, RN0);
+
+  load_word (State.regs[srci] + State.regs[srcm]);
+}
+
+// 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
+8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
+"dcpf"
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+
+  srcreg = translate_rreg (SD_, RN2);
+
+  load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
+8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
+"dcpf"
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+
+  srcreg = translate_rreg (SD_, RN2);
+
+  load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
+						     IMM24B, IMM24C)));
+}
+
+// 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
+8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
+"dcpf"
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+
+  srcreg = translate_rreg (SD_, RN2);
+
+  load_word (State.regs[srcreg]
+	     + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// bit operations with imm8,(abs16) addressing mode:
+
+// 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
+8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
+"btst"
+*am33_2
+{
+  PC = cia;
+  genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
+}
+
+// 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
+8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
+"bset"
+*am33_2
+{
+  unsigned32 temp;
+  int z;
+  
+  PC = cia;
+  temp = load_byte (FETCH16 (IMM16A, IMM16B));
+  z = (temp & IMM8) == 0;
+  temp |= IMM8;
+  store_byte (FETCH16 (IMM16A, IMM16B), temp);
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= (z ? PSW_Z : 0);
+}
+
+// 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
+8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
+"bclr"
+*am33_2
+{
+  unsigned32 temp;
+  int z;
+  
+  PC = cia;
+  temp = load_byte (FETCH16 (IMM16A, IMM16B));
+  z = (temp & IMM8) == 0;
+  temp = temp & ~(IMM8);
+  store_byte (FETCH16 (IMM16A, IMM16B), temp);
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= (z ? PSW_Z : 0);
+}
+
+// single precision fmov:
+
+// 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
+8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X,Sn) = load_word (State.regs[reg]);
+    }
+}
+
+// 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
+8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X,Sn) = load_word (State.regs[reg]);
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
+8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      XS2FS (X,Sn) = load_word (State.regs[reg]);
+    }
+}
+
+// 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
+8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X,Sn) = State.regs[reg];
+    }
+}
+
+// 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
+8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg], XS2FS (Y,Sm));
+    }
+}
+
+// 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
+8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg], XS2FS (Y,Sm));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
+8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_word (State.regs[reg], XS2FS (Y,Sm));
+    }
+}
+
+// 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
+8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      State.regs[reg] = XS2FS (Y,Sm);
+    }
+}
+
+// 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
+8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    XS2FS (X,Sn) = XS2FS (Y,Sm);
+}
+
+// 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
+8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+    }
+}
+
+// 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
+8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
+8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
+    }
+}
+
+// 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
+8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int ri = translate_rreg (SD_, Ri);
+      int rm = translate_rreg (SD_, Rm);
+      XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
+    }
+}
+
+// 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
+8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+    }
+}
+
+// 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
+8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
+8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
+    }
+}
+
+// 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
+8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int ri = translate_rreg (SD_, Ri);
+      int rm = translate_rreg (SD_, Rm);
+      store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
+    }
+}
+
+// 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
+8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X, Sn) = load_word (State.regs[reg]
+				 + EXTEND24 (FETCH24 (IMM24A,
+						      IMM24B, IMM24C)));
+    }
+}
+
+// 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
+8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X, Sn) = load_word (State.regs[reg]
+				 + EXTEND24 (FETCH24 (IMM24A,
+						      IMM24B, IMM24C)));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
+8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
+							    IMM24B, IMM24C));
+    }
+}
+
+// 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
+8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg]
+		  + EXTEND24 (FETCH24 (IMM24A,
+				       IMM24B, IMM24C)), XS2FS (Y, Sm));
+    }
+}
+
+// 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
+8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg]
+		  + EXTEND24 (FETCH24 (IMM24A,
+				       IMM24B, IMM24C)), XS2FS (Y, Sm));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
+8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_word (State.regs[reg]
+		  + FETCH24 (IMM24A,
+			     IMM24B, IMM24C), XS2FS (Y, Sm));
+    }
+}
+
+// 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
+8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X, Sn) = load_word (State.regs[reg]
+				 + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+						      IMM32C, IMM32D)));
+    }
+}
+
+// 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
+8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      XS2FS (X, Sn) = load_word (State.regs[reg]
+				 + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+						      IMM32C, IMM32D)));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
+8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      XS2FS (X, Sn) = load_word (State.regs[reg]
+				 + FETCH32 (IMM32A, IMM32B,
+					    IMM32C, IMM32D));
+    }
+}
+
+// 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
+8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
+8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg]
+		  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+				       IMM32C, IMM32D)), XS2FS (Y, Sm));
+    }
+}
+
+// 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
+8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_word (State.regs[reg]
+		  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+				       IMM32C, IMM32D)), XS2FS (Y, Sm));
+      State.regs[reg] += 4;
+    }
+}
+
+// 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
+8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_word (State.regs[reg]
+		  + FETCH32 (IMM32A, IMM32B,
+			     IMM32C, IMM32D), XS2FS (Y, Sm));
+    }
+}
+
+// double precision fmov:
+
+// 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
+8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X,fn) = load_dword (State.regs[reg]);
+    }
+}
+
+// 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
+8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X,fn) = load_dword (State.regs[reg]);
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
+8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      Xf2FD (X,fn) = load_dword (State.regs[reg]);
+    }
+}
+
+// 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
+8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg], Xf2FD (Y,fm));
+    }
+}
+
+// 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
+8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg], Xf2FD (Y,fm));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
+8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_dword (State.regs[reg], Xf2FD (Y,fm));
+    }
+}
+
+// 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
+8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
+8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int ri = translate_rreg (SD_, Ri);
+      int rm = translate_rreg (SD_, Rm);
+      Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
+    }
+}
+      
+// 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
+8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int ri = translate_rreg (SD_, Ri);
+      int rn = translate_rreg (SD_, Rn);
+      store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
+    }
+}
+      
+// 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
+8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+    }
+}
+
+// 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
+8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
+8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
+    }
+}
+
+// 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
+8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+    }
+}
+
+// 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
+8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
+8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
+    }
+}
+
+// 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
+8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X, fn) = load_dword (State.regs[reg]
+				  + EXTEND24 (FETCH24 (IMM24A,
+						       IMM24B, IMM24C)));
+    }
+}
+
+// 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
+8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X, fn) = load_dword (State.regs[reg]
+				  + EXTEND24 (FETCH24 (IMM24A,
+						       IMM24B, IMM24C)));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
+8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      Xf2FD (X, fn) = load_dword (State.regs[reg]
+				  + FETCH24 (IMM24A,
+					     IMM24B, IMM24C));
+    }
+}
+
+// 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
+8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg]
+		   + EXTEND24 (FETCH24 (IMM24A,
+					IMM24B, IMM24C)), Xf2FD (Y, fm));
+    }
+}
+
+// 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
+8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg]
+		   + EXTEND24 (FETCH24 (IMM24A,
+					IMM24B, IMM24C)), Xf2FD (Y, fm));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
+8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_dword (State.regs[reg] + FETCH24 (IMM24A,
+					      IMM24B, IMM24C), Xf2FD (Y, fm));
+    }
+}
+
+// 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
+8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X, fn) = load_dword (State.regs[reg]
+				  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+						       IMM32C, IMM32D)));
+    }
+}
+
+// 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
+8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      Xf2FD (X, fn) = load_dword (State.regs[reg]
+				  + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+						       IMM32C, IMM32D)));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
+8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      Xf2FD (X, fn) = load_dword (State.regs[reg]
+				  + FETCH32 (IMM32A, IMM32B,
+					     IMM32C, IMM32D));
+    }
+}
+
+// 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
+8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg]
+		   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+					IMM32C, IMM32D)), Xf2FD (Y, fm));
+    }
+}
+
+// 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
+8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      store_dword (State.regs[reg]
+		   + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+					IMM32C, IMM32D)), Xf2FD (Y, fm));
+      State.regs[reg] += 8;
+    }
+}
+
+// 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
+8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = REG_SP;
+      store_dword (State.regs[reg]
+		   + FETCH32 (IMM32A, IMM32B,
+			      IMM32C, IMM32D), Xf2FD (Y, fm));
+    }
+}
+
+// FPCR fmov:
+
+// 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
+8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rm);
+      unsigned32 val = State.regs[reg];
+      FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+	| ((FPCR & ~val) & EF_MASK);
+    }
+}
+
+// 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
+8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      int reg = translate_rreg (SD_, Rn);
+      State.regs[reg] = FPCR & FPCR_MASK;
+    }
+}
+
+// 1111 1101 1011 0101 imm32; fmov imm32,FPCR
+8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
+"fmov"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+	| ((FPCR & ~val) & EF_MASK);
+    }
+}
+
+// fabs:
+
+// 1111 1001 0100 010X ---- Sn..; fabs FSn
+8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
+"fabs"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      sim_fpu in, out;
+
+      FS2FPU (XS2FS (X,Sn), in);
+      sim_fpu_abs (&out, &in);
+      FPU2FS (out, XS2FS (X,Sn));
+    }
+}
+
+// 1111 1001 1100 010X ---- Sn..; fabs FDn
+8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
+"fabs"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
+8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
+"fabs"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      sim_fpu in, out;
+
+      FS2FPU (XS2FS (X,Sm), in);
+      sim_fpu_abs (&out, &in);
+      FPU2FS (out, XS2FS (Z,Sn));
+    }
+}
+
+// 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
+8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
+"fabs"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0100 011X ---- Sn..; fneg FSn
+8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
+"fneg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      sim_fpu in, out;
+
+      FS2FPU (XS2FS (X,Sn), in);
+      sim_fpu_neg (&out, &in);
+      FPU2FS (out, XS2FS (X,Sn));
+    }
+}
+
+// 1111 1001 1100 011X ---- Sn..; fneg FDn
+8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
+"fneg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
+8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
+"fneg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      sim_fpu in, out;
+
+      FS2FPU (XS2FS (X,Sm), in);
+      sim_fpu_neg (&out, &in);
+      FPU2FS (out, XS2FS (Z,Sn));
+    }
+}
+
+// 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
+8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
+"fneg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 000X ---- Sn..; frsqrt FSn
+8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
+"frsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1101 000X ---- fn.-; frsqrt FDn
+8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
+"frsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
+8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
+"frsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
+8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
+"frsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 001X ---- Sn..; fsqrt FSn
+8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
+"fsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 1101 001X ---- fn.-; fsqrt FDn
+8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
+"fsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
+8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
+"fsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
+8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
+"fsqrt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
+8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
+"fcmp"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
+}
+
+// 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
+8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
+"fcmp"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
+8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
+"fcmp"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+      fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
+    }
+}
+
+// 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
+8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
+"fadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_add (SD, CPU, cia,
+	     &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
+8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
+"fadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
+8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
+"fadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_add (SD, CPU, cia,
+	     &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
+8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
+"fadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
+8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
+"fadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+      fpu_add (SD, CPU, cia,
+	       &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+    }
+}
+
+// 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
+8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
+"fsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_sub (SD, CPU, cia,
+	     &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
+8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
+"fsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
+8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
+"fsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_sub (SD, CPU, cia,
+	     &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
+8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
+"fsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
+8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
+"fsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+      fpu_sub (SD, CPU, cia,
+	       &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+    }
+}
+
+// 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
+8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
+"fmul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_mul (SD, CPU, cia,
+	     &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
+8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
+"fmul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
+8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
+"fmul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_mul (SD, CPU, cia,
+	     &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
+8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
+"fmul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
+8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
+"fmul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+      fpu_mul (SD, CPU, cia,
+	       &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+    }
+}
+
+// 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
+8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
+"fdiv"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_div (SD, CPU, cia,
+	     &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
+8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
+"fdiv"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
+8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
+"fdiv"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_div (SD, CPU, cia,
+	     &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
+8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
+"fdiv"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
+8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
+"fdiv"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    {
+      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+      fpu_div (SD, CPU, cia,
+	       &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+    }
+}
+
+// 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
+"fmadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_fmadd (SD, CPU, cia,
+	       &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+	       &AS2FS (A,Sn), FP_SINGLE);
+}
+    
+// 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
+"fmsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_fmsub (SD, CPU, cia,
+	       &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+	       &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
+"fnmadd"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_fnmadd (SD, CPU, cia,
+		&XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+		&AS2FS (A,Sn), FP_SINGLE);
+}
+    
+// 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
+"fnmsub"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_fnmsub (SD, CPU, cia,
+		&XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+		&AS2FS (A,Sn), FP_SINGLE);
+}
+
+// conversion:
+
+// 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
+8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
+"ftoi"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
+8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
+"itof"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
+8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
+"ftod"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
+8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
+"dtof"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else
+    fpu_unimp_exception (SD, CPU, cia);
+}
+
+// branching:
+
+// 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd0+8.D8:D1:::fbeq
+"fbeq"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_E))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd1+8.D8:D1:::fbne
+"fbne"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd2+8.D8:D1:::fbgt
+"fbgt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_G))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd3+8.D8:D1:::fbge
+"fbge"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_G | FCC_E)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd4+8.D8:D1:::fblt
+"fblt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_L))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd5+8.D8:D1:::fble
+"fble"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_L | FCC_E)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd6+8.D8:D1:::fbuo
+"fbuo"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_U))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd7+8.D8:D1:::fblg
+"fblg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_L | FCC_G)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+// 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd8+8.D8:D1:::fbleg
+"fbleg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd9+8.D8:D1:::fbug
+"fbug"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_G)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xda+8.D8:D1:::fbuge
+"fbuge"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdb+8.D8:D1:::fbul
+"fbul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_L)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdc+8.D8:D1:::fbule
+"fbule"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdd+8.D8:D1:::fbue
+"fbue"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_E)))
+    {
+      State.regs[REG_PC] += EXTEND8 (D8);
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0000; fleq
+8.0xf0+8.0xd0:D0:::fleq
+"fleq"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_E))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0001; flne
+8.0xf0+8.0xd1:D0:::flne
+"flne"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0010; flgt
+8.0xf0+8.0xd2:D0:::flgt
+"flgt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_G))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0011; flge
+8.0xf0+8.0xd3:D0:::flge
+"flge"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_G | FCC_E)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0100; fllt
+8.0xf0+8.0xd4:D0:::fllt
+"fllt"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_L))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0101; flle
+8.0xf0+8.0xd5:D0:::flle
+"flle"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_L | FCC_E)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0110; fluo
+8.0xf0+8.0xd6:D0:::fluo
+"fluo"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & FCC_U))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 0111; fllg
+8.0xf0+8.0xd7:D0:::fllg
+"fllg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_L | FCC_G)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+// 1111 0000 1101 1000; flleg
+8.0xf0+8.0xd8:D0:::flleg
+"flleg"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 1001; flug
+8.0xf0+8.0xd9:D0:::flug
+"flug"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_G)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 1010; fluge
+8.0xf0+8.0xda:D0:::fluge
+"fluge"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 1011; flul
+8.0xf0+8.0xdb:D0:::flul
+"flul"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_L)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 1100; flule
+8.0xf0+8.0xdc:D0:::flule
+"flule"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0000 1101 1101; flue
+8.0xf0+8.0xdd:D0:::flue
+"flue"
+*am33_2
+{
+  PC = cia;
+
+  if (FPU_DISABLED)
+    fpu_disabled_exception (SD, CPU, cia);
+  else if ((FPCR & (FCC_U | FCC_E)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
Index: sim/mn10300/am33.igen
===================================================================
RCS file: /cvs/src/src/sim/mn10300/am33.igen,v
retrieving revision 1.8
diff -u -p -r1.8 am33.igen
--- sim/mn10300/am33.igen 26 Feb 2003 23:27:09 -0000 1.8
+++ sim/mn10300/am33.igen 26 Jun 2004 22:16:00 -0000
@@ -42,6 +42,7 @@
 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_USP];
@@ -52,6 +53,7 @@
 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
@@ -62,6 +64,7 @@
 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
@@ -72,6 +75,7 @@
 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = PC;
@@ -82,6 +86,7 @@
 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_USP] = State.regs[REG_A0 + AM1];
@@ -91,6 +96,7 @@
 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
@@ -100,6 +106,7 @@
 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
@@ -110,6 +117,7 @@
 8.0xf0+4.0xe,IMM4:D0t:::syscall
 "syscall"
 *am33
+*am33_2
 {
   unsigned32 sp, next_pc;
 
@@ -127,6 +135,7 @@
 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_D0 + DN0] = PSW;
@@ -137,6 +146,7 @@
 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   PSW = State.regs[REG_D0 + DM1];
@@ -146,6 +156,7 @@
 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RN0);
 
@@ -157,6 +168,7 @@
 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RN0);
 
@@ -168,6 +180,7 @@
 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RM1);
 
@@ -179,6 +192,7 @@
 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RM1);
 
@@ -191,6 +205,7 @@
 8.0xf8+8.0xce+8.REGS:D1a:::movm
 "movm"
 *am33
+*am33_2
 {
   unsigned32 usp = State.regs[REG_USP];
   unsigned32 mask;
@@ -242,6 +257,7 @@
     }
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x1)
@@ -283,6 +299,7 @@
 8.0xf8+8.0xcf+8.REGS:D1b:::movm
 "movm"
 *am33
+*am33_2
 {
   unsigned32 usp = State.regs[REG_USP];
   unsigned32 mask;
@@ -291,6 +308,7 @@
   mask = REGS;
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -375,6 +393,7 @@
 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
 "and"
 *am33
+*am33_2
 {
   PC = cia;
   PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -384,6 +403,7 @@
 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
 "or"
 *am33
+*am33_2
 {
   PC = cia;
   PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -393,6 +413,7 @@
 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -407,6 +428,7 @@
 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -422,6 +444,7 @@
 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
 "extb"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -435,6 +458,7 @@
 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
 "extbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -448,6 +472,7 @@
 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
 "exth"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -461,6 +486,7 @@
 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
 "exthu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -474,6 +500,7 @@
 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
 "clr"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -488,6 +515,7 @@
 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
 "add"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -501,6 +529,7 @@
 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
 "addc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, c, n, v;
@@ -530,6 +559,7 @@
 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
 "sub"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -543,6 +573,7 @@
 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
 "subc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, c, n, v;
@@ -572,6 +603,7 @@
 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
 "inc"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -584,6 +616,7 @@
 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
 "inc4"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -596,6 +629,7 @@
 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
 
@@ -609,6 +643,7 @@
 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg, srcreg;
 
@@ -623,6 +658,7 @@
 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -637,6 +673,7 @@
 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
 "and"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -657,6 +694,7 @@
 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
 "or"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -676,6 +714,7 @@
 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
 "xor"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -695,6 +734,7 @@
 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
 "not"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -713,6 +753,7 @@
 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
 "asr"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   signed32 temp;
@@ -736,6 +777,7 @@
 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n, c;
@@ -757,6 +799,7 @@
 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
 "asl"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -776,6 +819,7 @@
 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
 "asl2"
 *am33
+*am33_2
 {
   int dstreg;
   int n, z;
@@ -794,6 +838,7 @@
 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
 "ror"
 *am33
+*am33_2
 {
   int dstreg;
   int c, n, z;
@@ -818,6 +863,7 @@
 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
 "rol"
 *am33
+*am33_2
 {
   int dstreg;
   int c, n, z;
@@ -842,6 +888,7 @@
 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
 "mul"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   unsigned64 temp;
@@ -865,6 +912,7 @@
 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   unsigned64 temp;
@@ -888,6 +936,7 @@
 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
 "div"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   signed64 temp;
@@ -913,6 +962,7 @@
 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
 "divu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   unsigned64 temp;
@@ -939,6 +989,7 @@
 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -952,6 +1003,7 @@
 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -965,6 +1017,7 @@
 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -978,6 +1031,7 @@
 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -991,6 +1045,7 @@
 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1004,6 +1059,7 @@
 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1017,6 +1073,7 @@
 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1031,6 +1088,7 @@
 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1045,6 +1103,7 @@
 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1057,6 +1116,7 @@
 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1069,6 +1129,7 @@
 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1081,6 +1142,7 @@
 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1093,6 +1155,7 @@
 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1105,6 +1168,7 @@
 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1117,6 +1181,7 @@
 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1131,6 +1196,7 @@
 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1146,6 +1212,7 @@
 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   signed64 temp, sum;
@@ -1174,6 +1241,7 @@
 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   unsigned64 temp, sum;
@@ -1202,6 +1270,7 @@
 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   signed32 temp, sum;
@@ -1225,6 +1294,7 @@
 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   signed64 temp, sum;
@@ -1248,6 +1318,7 @@
 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   signed64 temp, sum;
@@ -1276,6 +1347,7 @@
 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   signed64 temp, sum;
@@ -1304,6 +1376,7 @@
 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   signed32 temp, temp2, sum;
@@ -1329,6 +1402,7 @@
 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
   unsigned32 temp, temp2, sum;
@@ -1354,6 +1428,7 @@
 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   signed32 temp;
@@ -1374,6 +1449,7 @@
 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   unsigned32 temp;
@@ -1394,6 +1470,7 @@
 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
 "sat16"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int value, z, n;
@@ -1421,6 +1498,7 @@
 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
 "mcste"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1518,6 +1596,7 @@
 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
 "swap"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1535,6 +1614,7 @@
 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
 "swaph"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1552,6 +1632,7 @@
 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
 "swhw"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1567,6 +1648,7 @@
 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
 "bsch"
 *am33
+*am33_2
 {
   int temp, c, i;
   int srcreg, dstreg;
@@ -1606,6 +1688,7 @@
 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1618,6 +1701,7 @@
 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1630,6 +1714,7 @@
 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1642,6 +1727,7 @@
 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg, imm;
   int z, c, n, v;
@@ -1670,6 +1756,7 @@
 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1683,6 +1770,7 @@
 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
 "subc"
 *am33
+*am33_2
 {
   int imm, dstreg;
   int z, c, n, v;
@@ -1711,6 +1799,7 @@
 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1723,6 +1812,7 @@
 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1736,6 +1826,7 @@
 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1754,6 +1845,7 @@
 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1772,6 +1864,7 @@
 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1790,6 +1883,7 @@
 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
   signed32 temp;
@@ -1812,6 +1906,7 @@
 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -1831,6 +1926,7 @@
 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
 "asl"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1849,6 +1945,7 @@
 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned64 temp;
@@ -1871,6 +1968,7 @@
 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned64 temp;
@@ -1893,6 +1991,7 @@
 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1905,6 +2004,7 @@
 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1918,6 +2018,7 @@
 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1931,6 +2032,7 @@
 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1944,6 +2046,7 @@
 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1957,6 +2060,7 @@
 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1970,6 +2074,7 @@
 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1983,6 +2088,7 @@
 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1997,6 +2103,7 @@
 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2012,6 +2119,7 @@
 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2024,6 +2132,7 @@
 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2036,6 +2145,7 @@
 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2048,6 +2158,7 @@
 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2060,6 +2171,7 @@
 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2072,6 +2184,7 @@
 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2084,6 +2197,7 @@
 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2098,6 +2212,7 @@
 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2113,6 +2228,7 @@
 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -2140,6 +2256,7 @@
 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -2167,6 +2284,7 @@
 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -2194,6 +2312,7 @@
 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -2221,6 +2340,7 @@
 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -2248,6 +2368,7 @@
 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -2275,6 +2396,7 @@
 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
 "mcste"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2371,6 +2493,7 @@
 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
 "add"
 *am33
+*am33_2
 {
   int z, c, n, v;
   unsigned32 sum, source1, source2;
@@ -2401,6 +2524,7 @@
 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
 "addc"
 *am33
+*am33_2
 {
   int z, c, n, v;
   unsigned32 sum, source1, source2;
@@ -2431,6 +2555,7 @@
 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
 "sub"
 *am33
+*am33_2
 {
   int z, c, n, v;
   unsigned32 difference, source1, source2;
@@ -2461,6 +2586,7 @@
 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
 "subc"
 *am33
+*am33_2
 {
   int z, c, n, v;
   unsigned32 difference, source1, source2;
@@ -2491,6 +2617,7 @@
 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
 "and"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2513,6 +2640,7 @@
 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
 "or"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2535,6 +2663,7 @@
 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
 "xor"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2557,6 +2686,7 @@
 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
 "asr"
 *am33
+*am33_2
 {
   int z, c, n;
   signed32 temp;
@@ -2583,6 +2713,7 @@
 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int z, c, n;
   int srcreg1, srcreg2, dstreg;
@@ -2606,6 +2737,7 @@
 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
 "asl"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2628,6 +2760,7 @@
 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
 "mul"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp;
@@ -2655,6 +2788,7 @@
 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp;
@@ -2682,6 +2816,7 @@
 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2694,6 +2829,7 @@
 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2706,6 +2842,7 @@
 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2718,6 +2855,7 @@
 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2730,6 +2868,7 @@
 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2742,6 +2881,7 @@
 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2754,6 +2894,7 @@
 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
@@ -2768,6 +2909,7 @@
 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2782,6 +2924,7 @@
 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
@@ -2796,6 +2939,7 @@
 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2810,6 +2954,7 @@
 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
@@ -2824,6 +2969,7 @@
 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2838,6 +2984,7 @@
 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp;
@@ -2874,6 +3021,7 @@
 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp;
@@ -2910,6 +3058,7 @@
 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
   signed32 temp, sum;
@@ -2938,6 +3087,7 @@
 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
   signed32 temp, sum;
@@ -2966,6 +3116,7 @@
 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp, sum;
@@ -2996,6 +3147,7 @@
 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp, sum;
@@ -3026,6 +3178,7 @@
 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
   signed32 temp, temp2, sum;
@@ -3056,6 +3209,7 @@
 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
   signed32 temp, temp2, sum;
@@ -3086,6 +3240,7 @@
 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp;
@@ -3108,6 +3263,7 @@
 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
 "dmulhu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed64 temp;
@@ -3130,6 +3286,7 @@
 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
 "sat24"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int value, n, z;
@@ -3157,6 +3314,7 @@
 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
 "bsch"
 *am33
+*am33_2
 {
   int temp, c, i;
   int srcreg1, srcreg2, dstreg;
@@ -3196,6 +3354,7 @@
 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3208,6 +3367,7 @@
 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3220,6 +3380,7 @@
 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3232,6 +3393,7 @@
 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg, z, n, c, v;
   unsigned32 sum, imm, reg2;
@@ -3259,6 +3421,7 @@
 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3271,6 +3434,7 @@
 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
 "subc"
 *am33
+*am33_2
 {
   int dstreg, z, n, c, v;
   unsigned32 difference, imm, reg2;
@@ -3298,6 +3462,7 @@
 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3310,6 +3475,7 @@
 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3323,6 +3489,7 @@
 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3341,6 +3508,7 @@
 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3359,6 +3527,7 @@
 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3377,6 +3546,7 @@
 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
   signed32 temp;
@@ -3400,6 +3570,7 @@
 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -3419,6 +3590,7 @@
 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
 "asl"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -3437,6 +3609,7 @@
 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned64 temp;
@@ -3459,6 +3632,7 @@
 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned64 temp;
@@ -3481,6 +3655,7 @@
 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3493,6 +3668,7 @@
 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3508,6 +3684,7 @@
 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3522,6 +3699,7 @@
 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3537,6 +3715,7 @@
 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3551,6 +3730,7 @@
 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3566,6 +3746,7 @@
 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3580,6 +3761,7 @@
 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3594,6 +3776,7 @@
 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3609,6 +3792,7 @@
 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3622,6 +3806,7 @@
 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3635,6 +3820,7 @@
 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3648,6 +3834,7 @@
 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3661,6 +3848,7 @@
 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3674,6 +3862,7 @@
 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3687,6 +3876,7 @@
 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3701,6 +3891,7 @@
 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3715,6 +3906,7 @@
 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -3742,6 +3934,7 @@
 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -3769,6 +3962,7 @@
 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -3796,6 +3990,7 @@
 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -3823,6 +4018,7 @@
 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -3850,6 +4046,7 @@
 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg;
   signed64 temp, sum;
@@ -3877,6 +4074,7 @@
 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3889,6 +4087,7 @@
 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3902,6 +4101,7 @@
 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3914,6 +4114,7 @@
 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3927,6 +4128,7 @@
 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3939,6 +4141,7 @@
 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3952,6 +4155,7 @@
 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3964,6 +4168,7 @@
 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3976,6 +4181,7 @@
 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3988,6 +4194,7 @@
 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned32 imm, reg2, sum;
@@ -4016,6 +4223,7 @@
 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4028,6 +4236,7 @@
 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
 "subc"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned32 imm, reg2, difference;
@@ -4056,6 +4265,7 @@
 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4068,6 +4278,7 @@
 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4081,6 +4292,7 @@
 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4099,6 +4311,7 @@
 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4117,6 +4330,7 @@
 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4135,6 +4349,7 @@
 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
   signed32 temp;
@@ -4157,6 +4372,7 @@
 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -4176,6 +4392,7 @@
 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
 "asl"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -4194,6 +4411,7 @@
 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned64 temp;
@@ -4216,6 +4434,7 @@
 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
   unsigned64 temp;
@@ -4238,6 +4457,7 @@
 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4250,6 +4470,7 @@
 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4264,6 +4485,7 @@
 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4278,6 +4500,7 @@
 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4292,6 +4515,7 @@
 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4306,6 +4530,7 @@
 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4320,6 +4545,7 @@
 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4334,6 +4560,7 @@
 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4348,6 +4575,7 @@
 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4363,6 +4591,7 @@
 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4376,6 +4605,7 @@
 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4389,6 +4619,7 @@
 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4402,6 +4633,7 @@
 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4415,6 +4647,7 @@
 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4428,6 +4661,7 @@
 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4442,6 +4676,7 @@
 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4456,6 +4691,7 @@
 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4471,6 +4707,7 @@
 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed64 temp, sum;
@@ -4499,6 +4736,7 @@
 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed64 temp, sum;
@@ -4527,6 +4765,7 @@
 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed32 temp, sum;
@@ -4550,6 +4789,7 @@
 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed32 temp, sum;
@@ -4573,6 +4813,7 @@
 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed32 temp, sum;
@@ -4596,6 +4837,7 @@
 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed32 temp, sum;
@@ -4619,6 +4861,7 @@
 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed32 temp, temp2, sum;
@@ -4644,6 +4887,7 @@
 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg, imm;
   signed32 temp, temp2, sum;
@@ -4669,6 +4913,7 @@
 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int imm, dstreg;
   signed32 temp;
@@ -4689,6 +4934,7 @@
 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
 "dmulhu"
 *am33
+*am33_2
 {
   int imm, dstreg;
   signed32 temp;
@@ -4709,6 +4955,7 @@
 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4721,6 +4968,7 @@
 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4733,6 +4981,7 @@
 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4745,6 +4994,7 @@
 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4757,6 +5007,7 @@
 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4769,6 +5020,7 @@
 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4781,6 +5033,7 @@
 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -4800,6 +5053,7 @@
 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -4818,6 +5072,7 @@
 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -4837,6 +5092,7 @@
 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -4855,6 +5111,7 @@
 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4872,6 +5129,7 @@
 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -4888,6 +5146,7 @@
 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -4907,6 +5166,7 @@
 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -4925,6 +5185,7 @@
 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -4947,6 +5208,7 @@
 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -4968,6 +5230,7 @@
 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -4987,6 +5250,7 @@
 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5006,6 +5270,7 @@
 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5025,6 +5290,7 @@
 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5043,6 +5309,7 @@
 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5060,6 +5327,7 @@
 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5076,6 +5344,7 @@
 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5093,6 +5362,7 @@
 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5109,6 +5379,7 @@
 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5126,6 +5397,7 @@
 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5142,6 +5414,7 @@
 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed int temp;
@@ -5162,6 +5435,7 @@
 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed int temp;
@@ -5181,6 +5455,7 @@
 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5198,6 +5473,7 @@
 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5215,6 +5491,7 @@
 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5232,6 +5509,7 @@
 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5248,6 +5526,7 @@
 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5267,6 +5546,7 @@
 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5285,6 +5565,7 @@
 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5304,6 +5585,7 @@
 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5322,6 +5604,7 @@
 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5339,6 +5622,7 @@
 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5355,6 +5639,7 @@
 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5374,6 +5659,7 @@
 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5392,6 +5678,7 @@
 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5414,6 +5701,7 @@
 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5435,6 +5723,7 @@
 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5454,6 +5743,7 @@
 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5473,6 +5763,7 @@
 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5492,6 +5783,7 @@
 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5510,6 +5802,7 @@
 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5529,6 +5822,7 @@
 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5547,6 +5841,7 @@
 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5566,6 +5861,7 @@
 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5584,6 +5880,7 @@
 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5601,6 +5898,7 @@
 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5617,6 +5915,7 @@
 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5636,6 +5935,7 @@
 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5654,6 +5954,7 @@
 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5676,6 +5977,7 @@
 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5697,6 +5999,7 @@
 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5716,6 +6019,7 @@
 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5735,6 +6039,7 @@
 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5754,6 +6059,7 @@
 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -5772,6 +6078,7 @@
 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5790,6 +6097,7 @@
 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -5807,6 +6115,7 @@
 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5825,6 +6134,7 @@
 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -5842,6 +6152,7 @@
 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5858,6 +6169,7 @@
 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5873,6 +6185,7 @@
 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5891,6 +6204,7 @@
 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -5908,6 +6222,7 @@
 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5929,6 +6244,7 @@
 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -5949,6 +6265,7 @@
 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -5967,6 +6284,7 @@
 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -5985,6 +6303,7 @@
 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6003,6 +6322,7 @@
 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6020,6 +6340,7 @@
 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6036,6 +6357,7 @@
 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6051,6 +6373,7 @@
 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6067,6 +6390,7 @@
 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6082,6 +6406,7 @@
 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6098,6 +6423,7 @@
 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6113,6 +6439,7 @@
 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   signed int temp;
@@ -6132,6 +6459,7 @@
 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   signed int temp;
@@ -6150,6 +6478,7 @@
 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6166,6 +6495,7 @@
 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6182,6 +6512,7 @@
 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6198,6 +6529,7 @@
 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6213,6 +6545,7 @@
 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6231,6 +6564,7 @@
 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6248,6 +6582,7 @@
 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6266,6 +6601,7 @@
 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6283,6 +6619,7 @@
 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6299,6 +6636,7 @@
 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6314,6 +6652,7 @@
 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6332,6 +6671,7 @@
 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6349,6 +6689,7 @@
 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6370,6 +6711,7 @@
 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6390,6 +6732,7 @@
 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6408,6 +6751,7 @@
 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6426,6 +6770,7 @@
 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6444,6 +6789,7 @@
 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6461,6 +6807,7 @@
 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6479,6 +6826,7 @@
 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6496,6 +6844,7 @@
 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6514,6 +6863,7 @@
 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6531,6 +6881,7 @@
 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6547,6 +6898,7 @@
 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6562,6 +6914,7 @@
 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6580,6 +6933,7 @@
 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6597,6 +6951,7 @@
 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6618,6 +6973,7 @@
 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6638,6 +6994,7 @@
 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6656,6 +7013,7 @@
 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6674,6 +7032,7 @@
 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6692,6 +7051,7 @@
 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   int result1;
@@ -6709,6 +7069,7 @@
 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
 "and_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6728,6 +7089,7 @@
 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
 "and_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -6746,6 +7108,7 @@
 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
 "and_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6765,6 +7128,7 @@
 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
 "and_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -6783,6 +7147,7 @@
 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
 "and_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -6800,6 +7165,7 @@
 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
 "and_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -6816,6 +7182,7 @@
 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
 "and_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6835,6 +7202,7 @@
 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
 "and_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -6853,6 +7221,7 @@
 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
 "and_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6875,6 +7244,7 @@
 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
 "and_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -6896,6 +7266,7 @@
 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
 "and_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6915,6 +7286,7 @@
 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
 "and_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -6934,6 +7306,7 @@
 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
 "and_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -6953,6 +7326,7 @@
 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
 "and_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -6971,6 +7345,7 @@
 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
 "dmach_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -6995,6 +7370,7 @@
 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
 "dmach_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7018,6 +7394,7 @@
 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
 "dmach_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7042,6 +7419,7 @@
 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
 "dmach_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7065,6 +7443,7 @@
 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
 "dmach_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7089,6 +7468,7 @@
 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
 "dmach_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7112,6 +7492,7 @@
 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
 "dmach_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7136,6 +7517,7 @@
 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
 "dmach_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7159,6 +7541,7 @@
 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
 "dmach_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7185,6 +7568,7 @@
 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
 "dmach_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7210,6 +7594,7 @@
 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
 "dmach_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7234,6 +7619,7 @@
 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
 "dmach_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7258,6 +7644,7 @@
 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
 "dmach_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7282,6 +7669,7 @@
 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
 "dmach_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed32 temp, temp2, sum;
@@ -7305,6 +7693,7 @@
 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
 "xor_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7324,6 +7713,7 @@
 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
 "xor_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7342,6 +7732,7 @@
 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
 "xor_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7361,6 +7752,7 @@
 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
 "xor_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7379,6 +7771,7 @@
 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
 "xor_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7396,6 +7789,7 @@
 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
 "xor_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7412,6 +7806,7 @@
 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
 "xor_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7431,6 +7826,7 @@
 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
 "xor_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7449,6 +7845,7 @@
 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
 "xor_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7471,6 +7868,7 @@
 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
 "xor_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7492,6 +7890,7 @@
 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
 "xor_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7511,6 +7910,7 @@
 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
 "xor_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7530,6 +7930,7 @@
 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
 "xor_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7549,6 +7950,7 @@
 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
 "xor_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7567,6 +7969,7 @@
 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
 "swhw_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7586,6 +7989,7 @@
 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
 "swhw_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7605,6 +8009,7 @@
 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
 "swhw_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7625,6 +8030,7 @@
 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
 "swhw_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7644,6 +8050,7 @@
 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
 "swhw_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7662,6 +8069,7 @@
 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
 "swhw_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7679,6 +8087,7 @@
 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
 "swhw_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7699,6 +8108,7 @@
 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
 "swhw_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7718,6 +8128,7 @@
 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
 "swhw_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7741,6 +8152,7 @@
 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
 "swhw_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7763,6 +8175,7 @@
 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
 "swhw_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7783,6 +8196,7 @@
 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
 "swhw_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7803,6 +8217,7 @@
 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
 "swhw_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7823,6 +8238,7 @@
 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
 "swhw_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7842,6 +8258,7 @@
 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
 "or_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7861,6 +8278,7 @@
 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
 "or_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7879,6 +8297,7 @@
 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
 "or_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7898,6 +8317,7 @@
 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
 "or_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7916,6 +8336,7 @@
 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
 "or_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7933,6 +8354,7 @@
 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
 "or_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7949,6 +8371,7 @@
 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
 "or_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -7968,6 +8391,7 @@
 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
 "or_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -7986,6 +8410,7 @@
 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
 "or_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8008,6 +8433,7 @@
 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
 "or_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8029,6 +8455,7 @@
 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
 "or_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8048,6 +8475,7 @@
 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
 "or_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8067,6 +8495,7 @@
 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
 "or_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8086,6 +8515,7 @@
 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
 "or_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8104,6 +8534,7 @@
 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
 "sat16_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8129,6 +8560,7 @@
 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
 "sat16_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8153,6 +8585,7 @@
 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
 "sat16_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8178,6 +8611,7 @@
 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
 "sat16_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8202,6 +8636,7 @@
 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
 "sat16_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -8224,6 +8659,7 @@
 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
 "sat16_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -8245,6 +8681,7 @@
 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
 "sat16_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8270,6 +8707,7 @@
 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
 "sat16_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8294,6 +8732,7 @@
 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
 "sat16_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8322,6 +8761,7 @@
 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
 "sat16_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8349,6 +8789,7 @@
 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
 "sat16_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8374,6 +8815,7 @@
 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
 "sat16_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8399,6 +8841,7 @@
 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
 "sat16_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   int result1;
@@ -8424,6 +8867,7 @@
 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
 "sat16_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   int result1;
@@ -8448,6 +8892,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
 "mov_llt"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8469,6 +8914,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
 "mov_lgt"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8491,6 +8937,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
 "mov_lge"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8512,6 +8959,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
 "mov_lle"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8534,6 +8982,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
 "mov_lcs"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8555,6 +9004,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
 "mov_lhi"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8576,6 +9026,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
 "mov_lcc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8597,6 +9048,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
 "mov_lls"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8618,6 +9070,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
 "mov_leq"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8639,6 +9092,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
 "mov_lne"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8660,6 +9114,7 @@
 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
 "mov_lra"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8674,3 +9129,4 @@
   nia = PC;
 }
 
+:include::am33_2:am33-2.igen
Index: sim/mn10300/interp.c
===================================================================
RCS file: /cvs/src/src/sim/mn10300/interp.c,v
retrieving revision 1.4
diff -u -p -r1.4 interp.c
--- sim/mn10300/interp.c 26 Jun 2004 21:53:47 -0000 1.4
+++ sim/mn10300/interp.c 26 Jun 2004 22:16:00 -0000
@@ -322,6 +322,9 @@ sim_create_inferior (SIM_DESC sd,
   }
   CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
+    PSW |= PSW_FE;
+
   return SIM_RC_OK;
 }
 
@@ -546,3 +549,569 @@ mn10300_cpu_exception_resume(SIM_DESC sd
     }
   State.exc_suspended = 0; 
 }
+
+/* This is called when an FP instruction is issued when the FP unit is
+   disabled, i.e., the FE bit of PSW is zero.  It raises interrupt
+   code 0x1c0.  */
+void
+fpu_disabled_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+  sim_io_eprintf(sd, "FPU disabled exception\n");
+  program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called when the FP unit is enabled but one of the
+   unimplemented insns is issued.  It raises interrupt code 0x1c8.  */
+void
+fpu_unimp_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+  sim_io_eprintf(sd, "Unimplemented FPU instruction exception\n");
+  program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called at the end of any FP insns that may have triggered
+   FP exceptions.  If no exception is enabled, it returns immediately.
+   Otherwise, it raises an exception code 0x1d0.  */
+void
+fpu_check_signal_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+  if ((FPCR & EC_MASK) == 0)
+    return;
+
+  sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n",
+		 (FPCR & EC_V) ? "V" : "",
+		 (FPCR & EC_Z) ? "Z" : "",
+		 (FPCR & EC_O) ? "O" : "",
+		 (FPCR & EC_U) ? "U" : "",
+		 (FPCR & EC_I) ? "I" : "");
+  program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* Convert a 32-bit single-precision FP value in the target platform
+   format to a sim_fpu value.  */
+static void
+reg2val_32 (const void *reg, sim_fpu *val)
+{
+  FS2FPU (*(reg_t *)reg, *val);
+}
+
+/* Round the given sim_fpu value to single precision, following the
+   target platform rounding and denormalization conventions.  On
+   AM33/2.0, round_near is the only rounding mode.  */
+static int
+round_32 (sim_fpu *val)
+{
+  return sim_fpu_round_32 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 32-bit single-precision target
+   representation.  */
+static void
+val2reg_32 (const sim_fpu *val, void *reg)
+{
+  FPU2FS (*val, *(reg_t *)reg);
+}
+
+/* Define the 32-bit single-precision conversion and rounding uniform
+   interface.  */
+const struct fp_prec_t
+fp_single_prec = {
+  reg2val_32, round_32, val2reg_32
+};
+
+/* Convert a 64-bit double-precision FP value in the target platform
+   format to a sim_fpu value.  */
+static void
+reg2val_64 (const void *reg, sim_fpu *val)
+{
+  FD2FPU (*(dword *)reg, *val);
+}
+
+/* Round the given sim_fpu value to double precision, following the
+   target platform rounding and denormalization conventions.  On
+   AM33/2.0, round_near is the only rounding mode.  */
+int
+round_64 (sim_fpu *val)
+{
+  return sim_fpu_round_64 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 64-bit double-precision target
+   representation.  */
+static void
+val2reg_64 (const sim_fpu *val, void *reg)
+{
+  FPU2FD (*val, *(dword *)reg);
+}
+
+/* Define the 64-bit single-precision conversion and rounding uniform
+   interface.  */
+const struct fp_prec_t
+fp_double_prec = {
+  reg2val_64, round_64, val2reg_64
+};
+
+/* Define shortcuts to the uniform interface operations.  */
+#define REG2VAL(reg,val) (*ops->reg2val) (reg,val)
+#define ROUND(val) (*ops->round) (val)
+#define VAL2REG(val,reg) (*ops->val2reg) (val,reg)
+
+/* Check whether overflow, underflow or inexact exceptions should be
+   raised.  */
+int
+fpu_status_ok (sim_fpu_status stat)
+{
+  if ((stat & sim_fpu_status_overflow)
+      && (FPCR & EE_O))
+    FPCR |= EC_O;
+  else if ((stat & (sim_fpu_status_underflow | sim_fpu_status_denorm))
+	   && (FPCR & EE_U))
+    FPCR |= EC_U;
+  else if ((stat & (sim_fpu_status_inexact | sim_fpu_status_rounded))
+	   && (FPCR & EE_I))
+    FPCR |= EC_I;
+  else if (stat & ~ (sim_fpu_status_overflow
+		     | sim_fpu_status_underflow
+		     | sim_fpu_status_denorm
+		     | sim_fpu_status_inexact
+		     | sim_fpu_status_rounded))
+    abort ();
+  else
+    return 1;
+  return 0;
+}
+
+/* Implement a 32/64 bit reciprocal square root, signaling FP
+   exceptions when appropriate.  */
+void
+fpu_rsqrt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	   const void *reg_in, void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu in, med, out;
+
+  REG2VAL (reg_in, &in);
+  ROUND (&in);
+  FPCR &= ~ EC_MASK;
+  switch (sim_fpu_is (&in))
+    {
+    case SIM_FPU_IS_SNAN:
+    case SIM_FPU_IS_NNUMBER:
+    case SIM_FPU_IS_NINF:
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+      break;
+	    
+    case SIM_FPU_IS_QNAN:
+      VAL2REG (&sim_fpu_qnan, reg_out);
+      break;
+
+    case SIM_FPU_IS_PINF:
+      VAL2REG (&sim_fpu_zero, reg_out);
+      break;
+
+    case SIM_FPU_IS_PNUMBER:
+      {
+	/* Since we don't have a function to compute rsqrt directly,
+	   use sqrt and inv.  */
+	sim_fpu_status stat = 0;
+	stat |= sim_fpu_sqrt (&med, &in);
+	stat |= sim_fpu_inv (&out, &med);
+	stat |= ROUND (&out);
+	if (fpu_status_ok (stat))
+	  VAL2REG (&out, reg_out);
+      }
+      break;
+
+    case SIM_FPU_IS_NZERO:
+    case SIM_FPU_IS_PZERO:
+      if (FPCR & EE_Z)
+	FPCR |= EC_Z;
+      else
+	{
+	  /* Generate an INF with the same sign.  */
+	  sim_fpu_inv (&out, &in);
+	  VAL2REG (&out, reg_out);
+	}
+      break;
+
+    default:
+      abort ();
+    }
+
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+static inline reg_t
+cmp2fcc (int res)
+{
+  switch (res)
+    {
+    case SIM_FPU_IS_SNAN:
+    case SIM_FPU_IS_QNAN:
+      return FCC_U;
+      
+    case SIM_FPU_IS_NINF:
+    case SIM_FPU_IS_NNUMBER:
+    case SIM_FPU_IS_NDENORM:
+      return FCC_L;
+      
+    case SIM_FPU_IS_PINF:
+    case SIM_FPU_IS_PNUMBER:
+    case SIM_FPU_IS_PDENORM:
+      return FCC_G;
+      
+    case SIM_FPU_IS_NZERO:
+    case SIM_FPU_IS_PZERO:
+      return FCC_E;
+      
+    default:
+      abort ();
+    }
+}
+
+/* Implement a 32/64 bit FP compare, setting the FPCR status and/or
+   exception bits as specified.  */
+void
+fpu_cmp (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	 const void *reg_in1, const void *reg_in2,
+	 const struct fp_prec_t *ops)
+{
+  sim_fpu m, n;
+
+  REG2VAL (reg_in1, &m);
+  REG2VAL (reg_in2, &n);
+  FPCR &= ~ EC_MASK;
+  FPCR &= ~ FCC_MASK;
+  ROUND (&m);
+  ROUND (&n);
+  if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n))
+    {
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	FPCR |= FCC_U;
+    }
+  else
+    FPCR |= cmp2fcc (sim_fpu_cmp (&m, &n));
+
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP add, setting FP exception bits when
+   appropriate.  */
+void
+fpu_add (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	 const void *reg_in1, const void *reg_in2,
+	 void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m, n, r;
+
+  REG2VAL (reg_in1, &m);
+  REG2VAL (reg_in2, &n);
+  ROUND (&m);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+	  && sim_fpu_is (&n) == SIM_FPU_IS_NINF)
+      || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+	  && sim_fpu_is (&n) == SIM_FPU_IS_PINF))
+    {
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_add (&r, &m, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP sub, setting FP exception bits when
+   appropriate.  */
+void
+fpu_sub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	 const void *reg_in1, const void *reg_in2,
+	 void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m, n, r;
+
+  REG2VAL (reg_in1, &m);
+  REG2VAL (reg_in2, &n);
+  ROUND (&m);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+	  && sim_fpu_is (&n) == SIM_FPU_IS_PINF)
+      || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+	  && sim_fpu_is (&n) == SIM_FPU_IS_NINF))
+    {
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_sub (&r, &m, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP mul, setting FP exception bits when
+   appropriate.  */
+void
+fpu_mul (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	 const void *reg_in1, const void *reg_in2,
+	 void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m, n, r;
+
+  REG2VAL (reg_in1, &m);
+  REG2VAL (reg_in2, &n);
+  ROUND (&m);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is_infinity (&m) && sim_fpu_is_zero (&n))
+      || (sim_fpu_is_zero (&m) && sim_fpu_is_infinity (&n)))
+    {
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_mul (&r, &m, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP div, setting FP exception bits when
+   appropriate.  */
+void
+fpu_div (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	 const void *reg_in1, const void *reg_in2,
+	 void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m, n, r;
+
+  REG2VAL (reg_in1, &m);
+  REG2VAL (reg_in2, &n);
+  ROUND (&m);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n))
+      || (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n)))
+    {
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n)
+	   && (FPCR & EE_Z))
+    FPCR |= EC_Z;
+  else
+    {
+      sim_fpu_status stat = sim_fpu_div (&r, &m, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP madd, setting FP exception bits when
+   appropriate.  */
+void
+fpu_fmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	   const void *reg_in1, const void *reg_in2, const void *reg_in3,
+	   void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m1, m2, m, n, r;
+
+  REG2VAL (reg_in1, &m1);
+  REG2VAL (reg_in2, &m2);
+  REG2VAL (reg_in3, &n);
+  ROUND (&m1);
+  ROUND (&m2);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+      || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+    {
+    invalid_operands:
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+      if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+	  && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+	goto invalid_operands;
+
+      stat |= sim_fpu_add (&r, &m, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP msub, setting FP exception bits when
+   appropriate.  */
+void
+fpu_fmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	   const void *reg_in1, const void *reg_in2, const void *reg_in3,
+	   void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m1, m2, m, n, r;
+
+  REG2VAL (reg_in1, &m1);
+  REG2VAL (reg_in2, &m2);
+  REG2VAL (reg_in3, &n);
+  ROUND (&m1);
+  ROUND (&m2);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+      || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+    {
+    invalid_operands:
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+      if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+	  && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+	goto invalid_operands;
+
+      stat |= sim_fpu_sub (&r, &m, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmadd, setting FP exception bits when
+   appropriate.  */
+void
+fpu_fnmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	    const void *reg_in1, const void *reg_in2, const void *reg_in3,
+	    void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m1, m2, m, mm, n, r;
+
+  REG2VAL (reg_in1, &m1);
+  REG2VAL (reg_in2, &m2);
+  REG2VAL (reg_in3, &n);
+  ROUND (&m1);
+  ROUND (&m2);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+      || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+    {
+    invalid_operands:
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+      if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+	  && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+	goto invalid_operands;
+
+      stat |= sim_fpu_neg (&mm, &m);
+      stat |= sim_fpu_add (&r, &mm, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmsub, setting FP exception bits when
+   appropriate.  */
+void
+fpu_fnmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+	    const void *reg_in1, const void *reg_in2, const void *reg_in3,
+	    void *reg_out, const struct fp_prec_t *ops)
+{
+  sim_fpu m1, m2, m, mm, n, r;
+
+  REG2VAL (reg_in1, &m1);
+  REG2VAL (reg_in2, &m2);
+  REG2VAL (reg_in3, &n);
+  ROUND (&m1);
+  ROUND (&m2);
+  ROUND (&n);
+  FPCR &= ~ EC_MASK;
+  if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+      || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+      || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+    {
+    invalid_operands:
+      if (FPCR & EE_V)
+	FPCR |= EC_V;
+      else
+	VAL2REG (&sim_fpu_qnan, reg_out);
+    }
+  else
+    {
+      sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+      if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+	  && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+	goto invalid_operands;
+
+      stat |= sim_fpu_neg (&mm, &m);
+      stat |= sim_fpu_sub (&r, &mm, &n);
+      stat |= ROUND (&r);
+      if (fpu_status_ok (stat))
+	VAL2REG (&r, reg_out);
+    }
+  
+  fpu_check_signal_exception (sd, cpu, cia);
+}
Index: sim/mn10300/mn10300.igen
===================================================================
RCS file: /cvs/src/src/sim/mn10300/mn10300.igen,v
retrieving revision 1.4
diff -u -p -r1.4 mn10300.igen
--- sim/mn10300/mn10300.igen 7 May 2001 04:52:00 -0000 1.4
+++ sim/mn10300/mn10300.igen 26 Jun 2004 22:16:01 -0000
@@ -4,6 +4,7 @@
 :option:::hi-bit-nr:7
 :model:::mn10300:mn10300:
 :model:::am33:am33:
+:model:::am33_2:am33_2:
 
 // What do we do with an illegal instruction?
 :internal::::illegal:
@@ -17,6 +18,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /*  OP_8000 (); */
   signed32 immed = EXTEND8 (IMM8);
@@ -29,6 +31,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   PC = cia;
   /* OP_80 (); */
@@ -41,6 +44,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F1E0 (); */
   PC = cia;
@@ -53,6 +57,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F1D0 (); */
   PC = cia;
@@ -65,6 +70,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
    PC = cia;
    /* OP_9000 (); */
@@ -77,6 +83,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
    PC = cia;
    /* OP_90 (); */
@@ -89,6 +96,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_3C (); */
   PC = cia;
@@ -101,6 +109,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F2F0 (); */
   PC = cia;
@@ -113,6 +122,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F2E4 (); */
   PC = cia;
@@ -125,6 +135,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F2F3 (); */
   PC = cia;
@@ -137,6 +148,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F2E0 (); */
   PC = cia;
@@ -149,6 +161,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F2F2 (); */
   PC = cia;
@@ -161,6 +174,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_70 (); */
   PC = cia;
@@ -173,6 +187,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F80000 (); */
   PC = cia;
@@ -186,6 +201,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FA000000 (); */
   PC = cia;
@@ -199,6 +215,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FC000000 (); */
   PC = cia;
@@ -213,6 +230,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_5800 (); */
   PC = cia;
@@ -225,6 +243,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FAB40000 (); */
   PC = cia;
@@ -238,6 +257,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FCB40000 (); */
   PC = cia;
@@ -251,6 +271,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F300 (); */
   PC = cia;
@@ -264,6 +285,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_300000 (); */
   PC = cia;
@@ -275,6 +297,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FCA40000 (); */
   PC = cia;
@@ -287,6 +310,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F000 (); */
   PC = cia;
@@ -299,6 +323,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F82000 (); */
   PC = cia;
@@ -312,6 +337,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FA200000 (); */
   PC = cia;
@@ -326,6 +352,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FC200000 (); */
   PC = cia;
@@ -340,6 +367,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_5C00 (); */
   PC = cia;
@@ -353,6 +381,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FAB00000 (); */
   PC = cia;
@@ -366,6 +395,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FCB00000 (); */
   PC = cia;
@@ -380,6 +410,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F380 (); */
   PC = cia;
@@ -394,6 +425,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FAA00000 (); */
   PC = cia;
@@ -406,6 +438,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FCA00000 (); */
   PC = cia;
@@ -419,6 +452,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F8F000 (); */
   PC = cia;
@@ -432,6 +466,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_60 (); */
   PC = cia;
@@ -444,6 +479,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F81000 (); */
   PC = cia;
@@ -457,6 +493,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FA100000 (); */
   PC = cia;
@@ -470,6 +507,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FC100000 (); */
   PC = cia;
@@ -484,6 +522,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_4200 (); */
   PC = cia;
@@ -496,6 +535,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FA910000 (); */
   PC = cia;
@@ -509,6 +549,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FC910000 (); */
   PC = cia;
@@ -522,6 +563,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F340 (); */
   PC = cia;
@@ -535,6 +577,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_10000 (); */
   PC = cia;
@@ -547,6 +590,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FC810000 (); */
   PC = cia;
@@ -560,6 +604,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F010 (); */
   PC = cia;
@@ -572,6 +617,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_F83000 (); */
   PC = cia;
@@ -585,6 +631,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FA300000 (); */
   PC = cia;
@@ -598,6 +645,7 @@
 "mov"
 *mn10300
 *am33
+*am33_2
 {
   /* OP_FC300000 (); */
   PC = cia;
@@ -613,6 +661,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_4300 (); */
@@ -627,6 +676,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA900000 (); */
@@ -642,6 +692,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC900000 (); */
@@ -657,6 +708,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F3C0 (); */
@@ -672,6 +724,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA800000 (); */
@@ -687,6 +740,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC800000 (); */
@@ -702,6 +756,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8F400 (); */
@@ -717,6 +772,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_2C0000 (); */
@@ -734,6 +790,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCCC0000 (); */
@@ -751,6 +808,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_240000 (); */
@@ -768,6 +826,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
     /* OP_FCDC0000 (); */
@@ -782,6 +841,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F040 (); */
@@ -797,6 +857,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F84000 (); */
@@ -812,6 +873,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA400000 (); */
@@ -828,6 +890,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC400000 (); */
@@ -844,6 +907,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8B800 (); */
@@ -859,6 +923,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAB80000 (); */
@@ -875,6 +940,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCB80000 (); */
@@ -891,6 +957,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F400 (); */
@@ -907,6 +974,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_340000 (); */
@@ -921,6 +989,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCA80000 (); */
@@ -936,6 +1005,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F050 (); */
@@ -950,6 +1020,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F85000 (); */
@@ -965,6 +1036,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA500000 (); */
@@ -980,6 +1052,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC500000 (); */
@@ -996,6 +1069,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F89200 (); */
@@ -1010,6 +1084,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA920000 (); */
@@ -1025,6 +1100,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC920000 (); */
@@ -1040,6 +1116,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F440 (); */
@@ -1055,6 +1132,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_20000 (); */
@@ -1070,6 +1148,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC820000 (); */
@@ -1085,6 +1164,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F060 (); */
@@ -1100,6 +1180,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F86000 (); */
@@ -1115,6 +1196,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA600000 (); */
@@ -1131,6 +1213,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC600000 (); */
@@ -1147,6 +1230,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8BC00 (); */
@@ -1162,6 +1246,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FABC0000 (); */
@@ -1177,6 +1262,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCBC0000 (); */
@@ -1192,6 +1278,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F480 (); */
@@ -1207,6 +1294,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_380000 (); */
@@ -1221,6 +1309,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCAC0000 (); */
@@ -1236,6 +1325,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F070 (); */
@@ -1251,6 +1341,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F87000 (); */
@@ -1266,6 +1357,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA700000 (); */
@@ -1281,6 +1373,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC700000 (); */
@@ -1297,6 +1390,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F89300 (); */
@@ -1312,6 +1406,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FA930000 (); */
@@ -1327,6 +1422,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC930000 (); */
@@ -1342,6 +1438,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F4C0 (); */
@@ -1357,6 +1454,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_30000 (); */
@@ -1371,6 +1469,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FC830000 (); */
@@ -1386,6 +1485,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F2D0 (); */
@@ -1403,6 +1503,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_10 (); */
@@ -1417,6 +1518,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_14 (); */
@@ -1431,6 +1533,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_18 (); */
@@ -1445,6 +1548,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_1C (); */
@@ -1459,6 +1563,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_0 (); */
@@ -1476,6 +1581,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_E0 (); */
@@ -1489,6 +1595,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F160 (); */
@@ -1503,6 +1610,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F150 (); */
@@ -1517,6 +1625,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F170 (); */
@@ -1531,6 +1640,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_2800 (); */
@@ -1545,6 +1655,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAC00000 (); */
@@ -1559,6 +1670,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCC00000 (); */
@@ -1573,6 +1685,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_2000 (); */
@@ -1587,6 +1700,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAD00000 (); */
@@ -1601,6 +1715,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCD00000 (); */
@@ -1615,6 +1730,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8FE00 (); */
@@ -1633,6 +1749,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAFE0000 (); */
@@ -1651,6 +1768,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCFE0000 (); */
@@ -1669,6 +1787,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F140 (); */
@@ -1699,6 +1818,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F100 (); */
@@ -1712,6 +1832,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F120 (); */
@@ -1726,6 +1847,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F110 (); */
@@ -1740,6 +1862,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F130 (); */
@@ -1754,6 +1877,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCC40000 (); */
@@ -1768,6 +1892,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCD40000 (); */
@@ -1782,6 +1907,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F180 (); */
@@ -1812,6 +1938,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F240 (); */
@@ -1836,6 +1963,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F250 (); */
@@ -1860,6 +1988,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F260 (); */
@@ -1897,6 +2026,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F270 (); */
@@ -1933,6 +2063,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_40 (); */
@@ -1950,6 +2081,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_41 (); */
@@ -1964,6 +2096,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_50 (); */
@@ -1978,6 +2111,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   PC = cia;
@@ -1992,6 +2126,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   PC = cia;
@@ -2006,6 +2141,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F1A0 (); */
@@ -2020,6 +2156,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F190 (); */
@@ -2034,6 +2171,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   PC = cia;
@@ -2049,6 +2187,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   PC = cia;
@@ -2063,6 +2202,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAC80000 (); */
@@ -2078,6 +2218,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCC80000 (); */
@@ -2093,6 +2234,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAD80000 (); */
@@ -2108,6 +2250,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCD80000 (); */
@@ -2123,6 +2266,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F200 (); */
@@ -2143,6 +2287,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8E000 (); */
@@ -2163,6 +2308,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAE00000 (); */
@@ -2183,6 +2329,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCE00000 (); */
@@ -2204,6 +2351,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAFC0000 (); */
@@ -2219,6 +2367,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F210 (); */
@@ -2233,6 +2382,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8E400 (); */
@@ -2247,6 +2397,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAE40000 (); */
@@ -2261,6 +2412,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCE40000 (); */
@@ -2275,6 +2427,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAFD0000 (); */
@@ -2289,6 +2442,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F220 (); */
@@ -2303,6 +2457,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAE80000 (); */
@@ -2317,6 +2472,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCE80000 (); */
@@ -2331,6 +2487,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F230 (); */
@@ -2351,6 +2508,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8EC00 (); */
@@ -2365,6 +2523,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAEC0000 (); */
@@ -2379,6 +2538,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCEC0000 (); */
@@ -2394,6 +2554,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FE020000 (); */
@@ -2410,6 +2571,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAF80000 (); */
@@ -2425,6 +2587,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F080 (); */
@@ -2448,6 +2611,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FE000000 (); */
@@ -2471,6 +2635,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAF00000 (); */
@@ -2493,6 +2658,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F090 (); */
@@ -2516,6 +2682,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FE010000 (); */
@@ -2539,6 +2706,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAF40000 (); */
@@ -2561,6 +2729,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F2B0 (); */
@@ -2585,6 +2754,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8C800 (); */
@@ -2609,6 +2779,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F2A0 (); */
@@ -2631,6 +2802,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8C400 (); */
@@ -2652,6 +2824,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F290 (); */
@@ -2673,6 +2846,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8C000 (); */
@@ -2693,6 +2867,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_54 (); */
@@ -2713,6 +2888,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F284 (); */
@@ -2739,6 +2915,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F280 (); */
@@ -2765,6 +2942,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C800 (); */
@@ -2783,6 +2961,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C900 (); */
@@ -2801,6 +2980,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C100 (); */
@@ -2820,6 +3000,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C200 (); */
@@ -2838,6 +3019,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C300 (); */
@@ -2857,6 +3039,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C000 (); */
@@ -2875,6 +3058,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C500 (); */
@@ -2893,6 +3077,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C600 (); */
@@ -2911,6 +3096,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C700 (); */
@@ -2929,6 +3115,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_C400 (); */
@@ -2947,6 +3134,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8E800 (); */
@@ -2965,6 +3153,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8E900 (); */
@@ -2983,6 +3172,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8EA00 (); */
@@ -3001,6 +3191,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F8EB00 (); */
@@ -3019,6 +3210,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_CA00 (); */
@@ -3034,6 +3226,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D8 (); */
@@ -3052,6 +3245,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D9 (); */
@@ -3070,6 +3264,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D1 (); */
@@ -3089,6 +3284,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D2 (); */
@@ -3107,6 +3303,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D3 (); */
@@ -3126,6 +3323,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D0 (); */
@@ -3144,6 +3342,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D5 (); */
@@ -3162,6 +3361,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D6 (); */
@@ -3180,6 +3380,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D7 (); */
@@ -3198,6 +3399,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_D4 (); */
@@ -3216,6 +3418,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_DA (); */
@@ -3231,6 +3434,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_DB (); */
@@ -3246,6 +3450,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0F4 (); */
@@ -3260,6 +3465,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_CC0000 (); */
@@ -3274,6 +3480,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_DC000000 (); */
@@ -3288,6 +3495,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0F0 (); */
@@ -3309,6 +3517,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FAFF0000 (); */
@@ -3330,6 +3539,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FCFF0000 (); */
@@ -3351,6 +3561,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0FC (); */
@@ -3368,6 +3579,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0FD (); */
@@ -3387,6 +3599,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0FE (); */
@@ -3406,6 +3619,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0FF (); */
@@ -3420,6 +3634,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_CB (); */
@@ -3444,6 +3659,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F6F0 (); */
@@ -3465,6 +3681,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F600 (); */
@@ -3489,6 +3706,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F90000 (); */
@@ -3513,6 +3731,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FB000000 (); */
@@ -3537,6 +3756,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FD000000 (); */
@@ -3561,6 +3781,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F610 (); */
@@ -3585,6 +3806,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F91400 (); */
@@ -3609,6 +3831,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FB140000 (); */
@@ -3633,6 +3856,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FD140000 (); */
@@ -3657,6 +3881,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F640 (); */
@@ -3676,6 +3901,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F650 (); */
@@ -3695,6 +3921,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F670 (); */
@@ -3715,6 +3942,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_F0C0 (); */
@@ -3729,6 +3957,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_FF (); */
@@ -3742,6 +3971,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_CE00 (); */
@@ -3795,6 +4025,7 @@
     }
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x1)
@@ -3839,6 +4070,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_CF00 (); */
@@ -3849,6 +4081,7 @@
   mask = REGS;
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -3936,6 +4169,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_CD000000 (); */
@@ -3950,6 +4184,7 @@
   mask = REGS;
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -4043,6 +4278,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_DD000000 (); */
@@ -4058,6 +4294,7 @@
   mask = REGS;
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -4150,6 +4387,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_DF0000 (); */
@@ -4164,6 +4402,7 @@
   mask = REGS;
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
 
@@ -4253,6 +4492,7 @@
 *mn10300
 
 *am33
+*am33_2
 
 {
   /* OP_DE0000 (); */
@@ -4268,6 +4508,7 @@
   mask = REGS;
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
       )
     {
 
Index: sim/mn10300/mn10300_sim.h
===================================================================
RCS file: /cvs/src/src/sim/mn10300/mn10300_sim.h,v
retrieving revision 1.5
diff -u -p -r1.5 mn10300_sim.h
--- sim/mn10300/mn10300_sim.h 26 Jun 2004 21:53:47 -0000 1.5
+++ sim/mn10300/mn10300_sim.h 26 Jun 2004 22:16:01 -0000
@@ -6,6 +6,7 @@
 #include <limits.h>
 #include "gdb/remote-sim.h"
 #include "bfd.h"
+#include "sim-fpu.h"
 
 #ifndef INLINE
 #ifdef __GNUC__
@@ -53,6 +54,10 @@ typedef signed long int32;
 #  endif
 #endif
 
+typedef struct
+{
+  uint32 low, high;
+} dword;
 typedef uint32 reg_t;
 
 struct simops 
@@ -73,6 +78,11 @@ struct _state
   reg_t regs[32];		/* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
 				   lir, lar, mdrq, plus some room for processor
 				   specific regs.  */
+  union
+  {
+    reg_t fs[32]; /* FS0-31 */
+    dword fd[16]; /* FD0,2,...,30 */
+  } fpregs;
   uint8 *mem;			/* main memory */
   int exception;
   int exited;
@@ -123,6 +133,52 @@ extern struct simops Simops[];
 #define REG_MCRL 27
 #define REG_MCVF 28
 
+#define REG_FPCR 29
+
+#define FPCR (State.regs[REG_FPCR])
+
+#define FCC_MASK LSMASK (21, 18)
+#define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
+#define EC_MASK  LSMASK (14, 10)
+#define EE_MASK  LSMASK ( 9,  5)
+#define EF_MASK  LSMASK ( 4,  0)
+#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
+
+#define FCC_L LSBIT (21)
+#define FCC_G LSBIT (20)
+#define FCC_E LSBIT (19)
+#define FCC_U LSBIT (18)
+
+#define EC_V LSBIT (14)
+#define EC_Z LSBIT (13)
+#define EC_O LSBIT (12)
+#define EC_U LSBIT (11)
+#define EC_I LSBIT (10)
+
+#define EE_V LSBIT (9)
+#define EE_Z LSBIT (8)
+#define EE_O LSBIT (7)
+#define EE_U LSBIT (6)
+#define EE_I LSBIT (5)
+
+#define EF_V LSBIT (4)
+#define EF_Z LSBIT (3)
+#define EF_O LSBIT (2)
+#define EF_U LSBIT (1)
+#define EF_I LSBIT (0)
+
+#define PSW_FE LSBIT(20)
+#define FPU_DISABLED !(PSW & PSW_FE)
+
+#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
+#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
+#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
+
+#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
+#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
+#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
+#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
+
 #ifdef _WIN32
 #define SIGTRAP 5
 #define SIGQUIT 3
@@ -145,6 +201,20 @@ sim_core_read_unaligned_2 (STATE_CPU (si
 #define load_word(ADDR) \
 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 
+#define load_dword(ADDR) \
+u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
+				   PC, read_map, (ADDR)))
+
+static INLINE dword
+u642dw (unsigned64 dw)
+{
+  dword r;
+
+  r.low = (unsigned32)dw;
+  r.high = (unsigned32)(dw >> 32);
+  return r;
+}
+
 #define store_byte(ADDR, DATA) \
 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
 			    PC, write_map, (ADDR), (DATA))
@@ -158,6 +228,15 @@ sim_core_write_unaligned_2 (STATE_CPU (s
 #define store_word(ADDR, DATA) \
 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
 			    PC, write_map, (ADDR), (DATA))
+#define store_dword(ADDR, DATA) \
+sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
+			    PC, write_map, (ADDR), dw2u64 (DATA))
+
+static INLINE unsigned64
+dw2u64 (dword data)
+{
+  return data.low | (((unsigned64)data.high) << 32);
+}
 
 /* Function declarations.  */
 
@@ -192,3 +271,29 @@ void program_interrupt (SIM_DESC sd, sim
 void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+
+void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
+void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
+void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
+
+extern const struct fp_prec_t
+{
+  void (* reg2val) (const void *, sim_fpu *);
+  int (*  round)   (sim_fpu *);
+  void (* val2reg) (const sim_fpu *, void *);
+} fp_single_prec, fp_double_prec;
+
+#define FP_SINGLE (&fp_single_prec)
+#define FP_DOUBLE (&fp_double_prec)
+
+void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
+void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
-- 
Alexandre Oliva             http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer   aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist  oliva@{lsd.ic.unicamp.br, gnu.org}

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