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Re: STEP_SKIPS_DELAY question, sort of
Andrew Cagney wrote:
Earlier MIPS variants (at least) needed STEP_SKIPS_DELAY. When at ``0x0'', a hardware single-step would end up at ``foo''. That isn't your problem.
Since your hardware can single-step into a delay slot, can it also resume from the delay slot? An example of this is SPARC with its constantly shuffling PC/N[ext]PC -- the inferior is resumed with PC==0x2 N[ext]PC==foo.
I'm not sure I understand what you mean by "can resume" - it can resume from a delay slot, but when doing so the branch instruction (and the delay slot) is re-executed. I don't have an NPC, and AFAIK there's no information in the CPU registers that tells me whether the branch is taken or not (which seems consistent with the fact that the branch-instruction is re-executed).
Ok, I'm starting to understand the wierdness
The SPARC (using PC/NextPC) resumes from the delay slot so re-inserting
the breakpoint is safe - that branch instruction is never re-executed.
Your architecture isn't like this.
I think there is still some missing information. Given:
N+0: branch foo
N+2: nop
and PC==N+0, exactly what state information is available after doing a
single hardware single-step (PC and status registers)?
- If I understand things correctly, one h/w single-step gets PC==N+2 and
two h/w single-steps gets PC==foo. For that to work there must be some
additional state information lurking somewhere - a bit indicating
stopped in delay slot perhaphs?
- If there were a breakpoint at N+2, what state information would be
available then. If the breakpoint were then yanked, where would a
single-step end up - again additional state information is needed to
make this work?
Maybe this can be stated in even simpler terms than "don't re-insert a breakpoint on an instruction that's going to be restarted when we resume execution". Rather, "single-step twice before re-inserting a breakpoint we're currently stopped at".
GDB needs to know that its in such a state.
Andrew