Re: Incorrect DWARF-2 register numbers on PPC64?

[Mark Kettenis <kettenis at chello dot nl>]

   Date: Thu, 18 Dec 2003 17:58:42 -0500
   From: David Edelsohn <dje@watson.ibm.com>

   >>>>> Andrew Cagney writes:

   > Argh!  Someone teach GCC about the PPC64 DWARF register numbering
   > please!  Before it is too late!  Now it is using the PPC32 LR register
   > number, which just happens to be the PPC64 FPSCR register.

	   The 32-bit PowerPC System V ABI defines DWARF Register Number
   Mapping that does not appear to be implemented in GCC or GDB.  This issue
   probably requires more thought and discussion about whether PPC64 should
   be compatible with PPC32 or PPC64 should be compliant with the ABI or both
   PPC32 and PPC64 should be compliant with the ABI.

Ah, You're right.  I should have looked a little better.  So currently
GCC uses the same mapping for DWARF as it does for stabs.  Seems like
there is a problem with GDB; we do some remapping for stabs (see
rs6000-tdep.c:rs6000_stab_reg_to_regnum), but don't remap for DWARF.
We probably should at least fix that until things are cleared up.

Personally I find it a bit awkward to use a non-standard register
mapping if there is a mapping defined in the ABI, so I'm in favour of
using the mapping defined in the System V ABI.  I don't know if this
is possible though, since changing the mapping might break exception
handling[1].

Mark

[1] From casual inspection this doesn't seem to be the case.  The
   general purpose registers will still be mapped in the same way, and
   the return address column is encoded in the debug info itself.