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[commit] FRV Simulator Cycle Accurate Cache


Hi,

I've committed this patch which adds a check for higher priority requests in the same cache pipeline when checking for address interference. This addresses a problem which occurs when a request gets requeued because the wait registers (WARS, BARS, NARS) are full. In some cases the requeued request was getting requeued behind a lower priority request for the same cache line which was behind it originally. This change correctly causes the lower priority request to also be requeued.

Dave
2003-11-03  Dave Brolley  <brolley@redhat.com>

	* cache.c (address_interference): Check for higher priority requests
	in the same pipeline.

Index: sim/frv/cache.c
===================================================================
RCS file: /cvs/src/src/sim/frv/cache.c,v
retrieving revision 1.2
diff -c -p -r1.2 cache.c
*** sim/frv/cache.c	8 Oct 2003 18:19:32 -0000	1.2
--- sim/frv/cache.c	3 Nov 2003 18:29:00 -0000
*************** address_interference (FRV_CACHE *cache, 
*** 1109,1122 ****
  	    return 1;
  	}
        /* If this is not a WAR request, then yield to any WAR requests in
! 	 either pipeline.  */
        if (req->kind != req_WAR)
  	{
  	  for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
  	    {
  	      other_req = cache->pipeline[i].stages[j].request;
! 	      if (other_req != NULL && other_req->kind == req_WAR)
! 		return 1;
  	    }
  	}
      }
--- 1109,1131 ----
  	    return 1;
  	}
        /* If this is not a WAR request, then yield to any WAR requests in
! 	 either pipeline or to a higher priority request in the same pipeline.
!       */
        if (req->kind != req_WAR)
  	{
  	  for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
  	    {
  	      other_req = cache->pipeline[i].stages[j].request;
! 	      if (other_req != NULL)
! 		{
! 		  if (other_req->kind == req_WAR)
! 		    return 1;
! 		  if (i == pipe
! 		      && (address == (other_req->address & line_mask) 
! 			  || address == all_address)
! 		      && priority > other_req->priority)
! 		    return 1;
! 		}
  	    }
  	}
      }

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