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[RFA] some sh-sim clean-ups


2003-06-27  Michael Snyder  <msnyder@redhat.com>

	* gencode.c (op tab): Some fix-ups of refs and defs.
	(ocbi, ocbp): Cache not simulated, but may cause memory fault.
	(gensym_caselist): Add default case to switch statement.
	(expand_ppi_code): Add default case to switch statement.

Index: gencode.c
===================================================================
RCS file: /cvs/src/src/sim/sh/gencode.c,v
retrieving revision 1.6
diff -p -r1.6 gencode.c
*** gencode.c	27 Jun 2003 21:18:42 -0000	1.6
--- gencode.c	27 Jun 2003 23:49:17 -0000
*************** op tab[] =
*** 195,201 ****
      "SET_SR_T (0);",
    },
  
!   { "", "", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100",
      "div1 (R, m, n/*, T*/);",
    },
  
--- 195,201 ----
      "SET_SR_T (0);",
    },
  
!   { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", /* ? MVS */
      "div1 (R, m, n/*, T*/);",
    },
  
*************** op tab[] =
*** 346,352 ****
      "}",
    },
    /* sh2e */
!   { "", "", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
--- 346,352 ----
      "}",
    },
    /* sh2e */
!   { "", "n", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
*************** op tab[] =
*** 359,365 ****
      "}",
    },
    /* sh2e */
!   { "", "", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
--- 359,365 ----
      "}",
    },
    /* sh2e */
!   { "", "m", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
*************** op tab[] =
*** 372,378 ****
      "}",
    },
    /* sh2e */
!   { "", "", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
--- 372,378 ----
      "}",
    },
    /* sh2e */
!   { "", "m", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
*************** op tab[] =
*** 387,393 ****
      "}",
    },
    /* sh2e */
!   { "", "", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
--- 387,393 ----
      "}",
    },
    /* sh2e */
!   { "n", "n", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
*************** op tab[] =
*** 402,408 ****
      "}",
    },
    /* sh2e */
!   { "", "", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
--- 402,408 ----
      "}",
    },
    /* sh2e */
!   { "", "0m", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
*************** op tab[] =
*** 415,421 ****
      "}",
    },
    /* sh2e */
!   { "", "", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
--- 415,421 ----
      "}",
    },
    /* sh2e */
!   { "", "0n", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111",
      /* sh4 */
      "if (FPSCR_SZ) {",
      "  MA (2);",
*************** op tab[] =
*** 519,543 ****
      "/* FIXME: user mode */",
    },
  #endif
!   { "", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
      "MA (1);",
      "CREG (m) = RLAT (R[n]);",
      "R[n] += 4;",
      "/* FIXME: user mode */",
    },
!   { "", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111",
      "MA (1);",
      "SET_SR (RLAT (R[n]));",
      "R[n] += 4;",
      "/* FIXME: user mode */",
    },
!   { "", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111",
      "MA (1);",
      "SET_MOD (RLAT (R[n]));",
      "R[n] += 4;",
    },
  #if 0
!   { "", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
      "MA (1);",
      "DBR = RLAT (R[n]);",
      "R[n] += 4;",
--- 519,543 ----
      "/* FIXME: user mode */",
    },
  #endif
!   { "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
      "MA (1);",
      "CREG (m) = RLAT (R[n]);",
      "R[n] += 4;",
      "/* FIXME: user mode */",
    },
!   { "n", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111",
      "MA (1);",
      "SET_SR (RLAT (R[n]));",
      "R[n] += 4;",
      "/* FIXME: user mode */",
    },
!   { "n", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111",
      "MA (1);",
      "SET_MOD (RLAT (R[n]));",
      "R[n] += 4;",
    },
  #if 0
!   { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
      "MA (1);",
      "DBR = RLAT (R[n]);",
      "R[n] += 4;",
*************** op tab[] =
*** 556,562 ****
    { "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
      "SREG (m) = R[n];",
    },
!   { "", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
      "MA (1);",
      "SREG (m) = RLAT(R[n]);",
      "R[n] += 4;",
--- 556,562 ----
    { "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
      "SREG (m) = R[n];",
    },
!   { "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
      "MA (1);",
      "SREG (m) = RLAT(R[n]);",
      "R[n] += 4;",
*************** op tab[] =
*** 566,572 ****
      "SET_FPSCR(R[n]);",
    },
    /* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
!   { "", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
      "MA (1);",
      "SET_FPSCR (RLAT(R[n]));",
      "R[n] += 4;",
--- 566,572 ----
      "SET_FPSCR(R[n]);",
    },
    /* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
!   { "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
      "MA (1);",
      "SET_FPSCR (RLAT(R[n]));",
      "R[n] += 4;",
*************** op tab[] =
*** 576,587 ****
      "/* FIXME: XXX*/ abort();",
    },
  
!   { "", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
      "trap (255, R0, PC, memory, maskl, maskw, endianw);",
      "/* FIXME: mac.l support */",
    },
  
!   { "", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
      "macw(R0,memory,n,m,endianw);",
    },
  
--- 576,587 ----
      "/* FIXME: XXX*/ abort();",
    },
  
!   { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
      "trap (255, R0, PC, memory, maskl, maskw, endianw);",
      "/* FIXME: mac.l support */",
    },
  
!   { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
      "macw(R0,memory,n,m,endianw);",
    },
  
*************** op tab[] =
*** 607,613 ****
      "R[n] = RSBAT (R0 + R[m]);",
      "L (n);",
    },
!   { "n", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
      "MA (1);",
      "R[n] = RSBAT (R[m]);",
      "R[m] += 1;",
--- 607,613 ----
      "R[n] = RSBAT (R0 + R[m]);",
      "L (n);",
    },
!   { "nm", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
      "MA (1);",
      "R[n] = RSBAT (R[m]);",
      "R[m] += 1;",
*************** op tab[] =
*** 629,635 ****
      "MA (1);",
      "WBAT (R[n] + R0, R[m]);",
    },
!   { "", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
      "MA (1);",
      "R[n] -= 1;",
      "WBAT (R[n], R[m]);",
--- 629,635 ----
      "MA (1);",
      "WBAT (R[n] + R0, R[m]);",
    },
!   { "n", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
      "MA (1);",
      "R[n] -= 1;",
      "WBAT (R[n], R[m]);",
*************** op tab[] =
*** 683,689 ****
      "MA (1);",
      "WLAT (R0 + R[n], R[m]);",
    },
!   { "", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
      "MA (1) ;",
      "R[n] -= 4;",
      "WLAT (R[n], R[m]);",
--- 683,689 ----
      "MA (1);",
      "WLAT (R0 + R[n], R[m]);",
    },
!   { "n", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
      "MA (1) ;",
      "R[n] -= 4;",
      "WLAT (R[n], R[m]);",
*************** op tab[] =
*** 798,811 ****
      "R[n] = ~R[m];",
    },
  
!   { "0", "", "ocbi @<REG_N>", "0000nnnn10010011",
!     "/* FIXME: Not implemented */",
!     "RAISE_EXCEPTION (SIGILL);",
    },
  
!   { "0", "", "ocbp @<REG_N>", "0000nnnn10100011",
!     "/* FIXME: Not implemented */",
!     "RAISE_EXCEPTION (SIGILL);",
    },
  
    { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011",
--- 799,812 ----
      "R[n] = ~R[m];",
    },
  
!   { "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
!     "RSBAT (R[n]); /* Take exceptions like byte load.  */",
!     "/* FIXME: Cache not implemented */",
    },
  
!   { "", "n", "ocbp @<REG_N>", "0000nnnn10100011",
!     "RSBAT (R[n]); /* Take exceptions like byte load.  */",
!     "/* FIXME: Cache not implemented */",
    },
  
    { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011",
*************** op tab[] =
*** 880,886 ****
    { "", "n", "setrc <REG_N>", "0100nnnn00010100",
      "SET_RC (R[n]);",
    },
!   { "", "n", "setrc #<imm>", "10000010i8*1....",
      /* It would be more realistic to let loop_start point to some static
         memory that contains an illegal opcode and then give a bus error when
         the loop is eventually encountered, but it seems not only simpler,
--- 881,887 ----
    { "", "n", "setrc <REG_N>", "0100nnnn00010100",
      "SET_RC (R[n]);",
    },
!   { "", "", "setrc #<imm>", "10000010i8*1....",
      /* It would be more realistic to let loop_start point to some static
         memory that contains an illegal opcode and then give a bus error when
         the loop is eventually encountered, but it seems not only simpler,
*************** gensim_caselist (p)
*** 2137,2142 ****
--- 2138,2147 ----
  	{
  	  switch (*s)
  	    {
+               fprintf (stderr, "gencode/gensim_caselist: illegal char '%c'\n",
+                        *s);
+               exit (1);
+               break;
  	    case '0':
  	    case '1':
  	      s += 2;
*************** expand_ppi_code (val, i, s)
*** 2330,2335 ****
--- 2335,2345 ----
      {
        switch (s[0])
  	{
+         default:
+           fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n",
+                    s[0]);
+           exit (2);
+ 	  break;
  	/* The last eight bits are disregarded for the switch table.  */
  	case 'm':
  	case 'x':

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