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[RFA] H8 sim: add trapa, rte, rts/l, rte/l, VECIND...


Latest new stuff for the h8sx simulator.
2003-05-30  Michael Snyder  <msnyder@redhat.com>

	* compile.c (decode): Back out INDEXB and INDEXW changes from 5/23.
	(fetch_1): Ditto.

2003-05-29  Michael Snyder  <msnyder@redhat.com>

	* compile.c (sim_resume): H8SX can use any register for TAS.

2003-05-23  Michael Snyder  <msnyder@redhat.com>

	* compile.c: Replace "Hitachi" with "Renesas".
	(decode): Distinguish AV_H8S from AV_H8H.
	Make sure LOWREG and INDEXB and INDEXW all use low half of register.
	(fetch_1): Ditto.

	* compile.c (decode): Add support for VECIND.

2003-05-22  Michael Snyder  <msnyder@redhat.com>

	* compile.c (sim_resume): Implement rte/l and rts/l.

2003-05-21  Michael Snyder  <msnyder@redhat.com>

	* compile.c (GETSR): New macro (actually old macro reincarnated).
	(decode): Add handling for IMM2.
	(sim_resume): Drop extra block around jmp, jsr, rts.
	Add handling for trapa and rte.  
	(divxu.b): Change 0xffff mask to 0xff.

	* compile.c (sim_resume): divx[su].b apparently has a 16-bit
	dividend, despite what the H8SX manual says...

Index: compile.c
===================================================================
RCS file: /cvs/src/src/sim/h8300/compile.c,v
retrieving revision 1.27
diff -p -r1.27 compile.c
*** compile.c	3 Jun 2003 21:38:26 -0000	1.27
--- compile.c	3 Jun 2003 23:10:05 -0000
***************
*** 1,5 ****
  /*
!  * Simulator for the Hitachi H8/300 architecture.
   *
   * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
   *
--- 1,5 ----
  /*
!  * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
   *
   * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
   *
*************** enum { POLL_QUIT_INTERVAL = 0x80000 };
*** 484,489 ****
--- 484,501 ----
    h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4)	\
  	     | (N << 3) | (Z << 2) | (V << 1) | C)
  
+ #define GETSR(SD) \
+   /* Get Status Register (flags).  */		\
+   c = (h8_get_ccr (sd) >> 0) & 1;		\
+   v = (h8_get_ccr (sd) >> 1) & 1;		\
+   nz = !((h8_get_ccr (sd) >> 2) & 1);		\
+   n = (h8_get_ccr (sd) >> 3) & 1;		\
+   u = (h8_get_ccr (sd) >> 4) & 1;		\
+   h = (h8_get_ccr (sd) >> 5) & 1;		\
+   ui = ((h8_get_ccr (sd) >> 6) & 1);		\
+   intMaskBit = (h8_get_ccr (sd) >> 7) & 1
+ 
+ 
  #ifdef __CHAR_IS_SIGNED__
  #define SEXTCHAR(x) ((char) (x))
  #endif
*************** decode (SIM_DESC sd, int addr, unsigned 
*** 590,595 ****
--- 602,608 ----
        unsigned int len = 0;
  
        if ((q->available == AV_H8SX && !h8300sxmode) ||
+ 	  (q->available == AV_H8S  && !h8300smode)  ||
  	  (q->available == AV_H8H  && !h8300hmode))
  	continue;
  
*************** decode (SIM_DESC sd, int addr, unsigned 
*** 831,836 ****
--- 844,855 ----
  		{
  		  cst[opnum] = data[1];
  		}
+ 	      else if ((looking_for & MODE) == VECIND)
+ 		{
+ 		  /* FIXME: Multiplier should be 2 for "normal" mode.  */
+ 		  cst[opnum] = ((data[1] & 0x7f) + 0x80) * 4;
+ 		  cst[opnum] += h8_get_vbr (sd); /* Add vector base reg.  */
+ 		}
  	      else if ((looking_for & SIZE) == L_32)
  		{
  		  int i = len / 2;
*************** decode (SIM_DESC sd, int addr, unsigned 
*** 885,890 ****
--- 904,913 ----
  		      cst[opnum] = data[len / 2] & 0xff;
  		    }
  		}
+ 	      else if ((looking_for & SIZE) == L_2)
+ 		{
+ 		  cst[opnum] = thisnib & 3;
+ 		}
  	      else if ((looking_for & SIZE) == L_3 ||
  		       (looking_for & SIZE) == L_3NZ)
  		{
*************** decode (SIM_DESC sd, int addr, unsigned 
*** 1025,1031 ****
  			    else
  			      p->reg = ZERO_REGNUM;;
  			  }
! 			else if ((x & MODE) == MEMIND)
  			  {
  			    /* Size doesn't matter.  */
  			    p->type = X (OP_MEM, SB);
--- 1048,1055 ----
  			    else
  			      p->reg = ZERO_REGNUM;;
  			  }
! 			else if ((x & MODE) == MEMIND ||
! 				 (x & MODE) == VECIND)
  			  {
  			    /* Size doesn't matter.  */
  			    p->type = X (OP_MEM, SB);
*************** decode (SIM_DESC sd, int addr, unsigned 
*** 1104,1110 ****
  			    p->type = OP_EXR;
  			  }
  			else
! 			  printf ("Hmmmm %x...\n", x);
  
  			args++;
  		      }
--- 1128,1134 ----
  			    p->type = OP_EXR;
  			  }
  			else
! 			  printf ("Hmmmm 0x%x...\n", x);
  
  			args++;
  		      }
*************** decode (SIM_DESC sd, int addr, unsigned 
*** 1158,1164 ****
  		  return;
  		}
  	      else
! 		printf ("Don't understand %x \n", looking_for);
  	    }
  
  	  len++;
--- 1182,1188 ----
  		  return;
  		}
  	      else
! 		printf ("Don't understand 0x%x \n", looking_for);
  	    }
  
  	  len++;
*************** sim_resume (SIM_DESC sd, int step, int s
*** 1893,1906 ****
      }
  
    /* Get Status Register (flags).  */
!   c = (h8_get_ccr (sd) >> 0) & 1;
!   v = (h8_get_ccr (sd) >> 1) & 1;
!   nz = !((h8_get_ccr (sd) >> 2) & 1);
!   n = (h8_get_ccr (sd) >> 3) & 1;
!   u = (h8_get_ccr (sd) >> 4) & 1;
!   h = (h8_get_ccr (sd) >> 5) & 1;
!   ui = ((h8_get_ccr (sd) >> 6) & 1);
!   intMaskBit = (h8_get_ccr (sd) >> 7) & 1;
  
    if (h8300smode)	/* Get exr.  */
      {
--- 1917,1923 ----
      }
  
    /* Get Status Register (flags).  */
!   GETSR (sd);
  
    if (h8300smode)	/* Get exr.  */
      {
*************** sim_resume (SIM_DESC sd, int step, int s
*** 2197,2203 ****
  	    goto end;
  	  goto just_flags_log32;
  
! 	case O (O_MOVMD, SB):		/* movsd.b */
  	  ea = GET_W_REG (4);
  	  if (ea == 0)
  	    ea = 0x10000;
--- 2214,2220 ----
  	    goto end;
  	  goto just_flags_log32;
  
! 	case O (O_MOVMD, SB):		/* movmd.b */
  	  ea = GET_W_REG (4);
  	  if (ea == 0)
  	    ea = 0x10000;
*************** sim_resume (SIM_DESC sd, int step, int s
*** 2212,2218 ****
  	    }
  	  goto next;
  
! 	case O (O_MOVMD, SW):		/* movsd.b */
  	  ea = GET_W_REG (4);
  	  if (ea == 0)
  	    ea = 0x10000;
--- 2229,2235 ----
  	    }
  	  goto next;
  
! 	case O (O_MOVMD, SW):		/* movmd.w */
  	  ea = GET_W_REG (4);
  	  if (ea == 0)
  	    ea = 0x10000;
*************** sim_resume (SIM_DESC sd, int step, int s
*** 2227,2233 ****
  	    }
  	  goto next;
  
! 	case O (O_MOVMD, SL):		/* movsd.b */
  	  ea = GET_W_REG (4);
  	  if (ea == 0)
  	    ea = 0x10000;
--- 2244,2250 ----
  	    }
  	  goto next;
  
! 	case O (O_MOVMD, SL):		/* movmd.l */
  	  ea = GET_W_REG (4);
  	  if (ea == 0)
  	    ea = 0x10000;
*************** sim_resume (SIM_DESC sd, int step, int s
*** 3463,3498 ****
          case O (O_JMP, SL):
          case O (O_JMP, SB):		/* jmp */
          case O (O_JMP, SW):
! 	  {
! 	    fetch (sd, &code->src, &pc);
! 	    goto end;
! 	  }
  
  	case O (O_JSR, SN):
  	case O (O_JSR, SL):
  	case O (O_JSR, SB):		/* jsr, jump to subroutine */
  	case O (O_JSR, SW):
! 	  {
! 	    int tmp;
! 	    if (fetch (sd, &code->src, &pc))
! 	      goto end;
! 	  call:
! 	    tmp = h8_get_reg (sd, SP_REGNUM);
  
! 	    if (h8300hmode)
! 	      {
! 		tmp -= 4;
! 		SET_MEMORY_L (tmp, code->next_pc);
! 	      }
! 	    else
! 	      {
! 		tmp -= 2;
! 		SET_MEMORY_W (tmp, code->next_pc);
! 	      }
! 	    h8_set_reg (sd, SP_REGNUM, tmp);
  
! 	    goto end;
! 	  }
  
  	case O (O_BSR, SW):
  	case O (O_BSR, SL):
--- 3480,3510 ----
          case O (O_JMP, SL):
          case O (O_JMP, SB):		/* jmp */
          case O (O_JMP, SW):
! 	  fetch (sd, &code->src, &pc);
! 	  goto end;
  
  	case O (O_JSR, SN):
  	case O (O_JSR, SL):
  	case O (O_JSR, SB):		/* jsr, jump to subroutine */
  	case O (O_JSR, SW):
! 	  if (fetch (sd, &code->src, &pc))
! 	    goto end;
! 	call:
! 	  tmp = h8_get_reg (sd, SP_REGNUM);
  
! 	  if (h8300hmode)
! 	    {
! 	      tmp -= 4;
! 	      SET_MEMORY_L (tmp, code->next_pc);
! 	    }
! 	  else
! 	    {
! 	      tmp -= 2;
! 	      SET_MEMORY_W (tmp, code->next_pc);
! 	    }
! 	  h8_set_reg (sd, SP_REGNUM, tmp);
  
! 	  goto end;
  
  	case O (O_BSR, SW):
  	case O (O_BSR, SL):
*************** sim_resume (SIM_DESC sd, int step, int s
*** 3502,3527 ****
  	  pc = code->next_pc + res;
  	  goto call;
  
! 	case O (O_RTS, SN):		/* rts, return from subroutine */
! 	  {
! 	    int tmp;
  
! 	    tmp = h8_get_reg (sd, SP_REGNUM);
  
! 	    if (h8300hmode)
! 	      {
! 		pc = GET_MEMORY_L (tmp);
! 		tmp += 4;
! 	      }
! 	    else
! 	      {
! 		pc = GET_MEMORY_W (tmp);
! 		tmp += 2;
! 	      }
  
! 	    h8_set_reg (sd, SP_REGNUM, tmp);
! 	    goto end;
! 	  }
  
  	case O (O_ILL, SB):		/* illegal */
  	  sim_engine_set_run_state (sd, sim_stopped, SIGILL);
--- 3514,3565 ----
  	  pc = code->next_pc + res;
  	  goto call;
  
! 	case O (O_RTE, SN):		/* rte, return from exception */
! 	rte:
! 	  /* Pops exr and ccr before pc -- otherwise identical to rts.  */
! 	  tmp = h8_get_reg (sd, SP_REGNUM);
! 
! 	  if (h8300smode)			/* pop exr */
! 	    {
! 	      h8_set_exr (sd, GET_MEMORY_L (tmp));
! 	      tmp += 4;
! 	    }
! 	  if (h8300hmode)
! 	    {
! 	      h8_set_ccr (sd, GET_MEMORY_L (tmp));
! 	      tmp += 4;
! 	      pc = GET_MEMORY_L (tmp);
! 	      tmp += 4;
! 	    }
! 	  else
! 	    {
! 	      h8_set_ccr (sd, GET_MEMORY_W (tmp));
! 	      tmp += 2;
! 	      pc = GET_MEMORY_W (tmp);
! 	      tmp += 2;
! 	    }
  
! 	  GETSR (sd);
! 	  h8_set_reg (sd, SP_REGNUM, tmp);
! 	  goto end;
  
! 	case O (O_RTS, SN):		/* rts, return from subroutine */
! 	rts:
! 	  tmp = h8_get_reg (sd, SP_REGNUM);
  
! 	  if (h8300hmode)
! 	    {
! 	      pc = GET_MEMORY_L (tmp);
! 	      tmp += 4;
! 	    }
! 	  else
! 	    {
! 	      pc = GET_MEMORY_W (tmp);
! 	      tmp += 2;
! 	    }
! 
! 	  h8_set_reg (sd, SP_REGNUM, tmp);
! 	  goto end;
  
  	case O (O_ILL, SB):		/* illegal */
  	  sim_engine_set_run_state (sd, sim_stopped, SIGILL);
*************** sim_resume (SIM_DESC sd, int step, int s
*** 3544,3549 ****
--- 3582,3611 ----
  	    }
  	  goto end;
  
+ 	case O (O_TRAPA, SB):		/* trapa */
+ 	  if (fetch (sd, &code->src, &res))
+ 	    goto end;			/* res is vector number.  */
+ 
+ 	  tmp = h8_get_reg (sd, SP_REGNUM);
+ 	  tmp -= 4;
+ 	  SET_MEMORY_L (tmp, code->next_pc);
+ 	  tmp -= 4; 
+ 	  SET_MEMORY_L (tmp, h8_get_ccr (sd));
+ 	  intMaskBit = 1;
+ 	  BUILDSR (sd);
+ 
+ 	  if (h8300smode)
+ 	    {
+ 	      tmp -= 4;
+ 	      SET_MEMORY_L (tmp, h8_get_exr (sd));
+ 	    }
+ 
+ 	  h8_set_reg (sd, SP_REGNUM, tmp);
+ 
+ 	  /* FIXME: "normal" mode should use 2-byte ptrs.  */
+ 	  pc = GET_MEMORY_L (0x20 + res * 4);
+ 	  goto end;
+ 
  	case O (O_BPT, SN):
  	  sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
  	  goto end;
*************** sim_resume (SIM_DESC sd, int step, int s
*** 3898,3916 ****
  
  	  goto next;
  
! 	case O (O_TAS, SB):		/* tas, (test and set?) */
! 	  if (!h8300smode || code->src.type != X (OP_REG, SL))
! 	    goto illegal;
! 	  switch (code->src.reg)
! 	    {
! 	    case R0_REGNUM:
! 	    case R1_REGNUM:
! 	    case R4_REGNUM:
! 	    case R5_REGNUM:
! 	      break;
! 	    default:
! 	      goto illegal;
! 	    }
  	  if (fetch (sd, &code->src, &res))
  	    goto end;
  	  if (store (sd, &code->src, res | 0x80))
--- 3960,3978 ----
  
  	  goto next;
  
! 	case O (O_TAS, SB):		/* tas (test and set) */
! 	  if (!h8300sxmode)		/* h8sx can use any register. */
! 	    switch (code->src.reg)
! 	      {
! 	      case R0_REGNUM:
! 	      case R1_REGNUM:
! 	      case R4_REGNUM:
! 	      case R5_REGNUM:
! 		break;
! 	      default:
! 		goto illegal;
! 	      }
! 
  	  if (fetch (sd, &code->src, &res))
  	    goto end;
  	  if (store (sd, &code->src, res | 0x80))
*************** sim_resume (SIM_DESC sd, int step, int s
*** 4023,4029 ****
  	      res = 0;
  	    }
  
! 	  if (store (sd, &code->dst, (res & 0xffff) | (tmp << 8)))
  	    goto end;
  	  goto next;
  
--- 4085,4091 ----
  	      res = 0;
  	    }
  
! 	  if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
  	    goto end;
  	  goto next;
  
*************** sim_resume (SIM_DESC sd, int step, int s
*** 4190,4214 ****
  	  goto next;
  
  	case O (O_LDM, SL):			/* ldm,  load from memory */
  	  {
  	    int nregs, firstreg, i;
  
! 	    nregs = GET_MEMORY_B (pc + 1);
! 	    nregs >>= 4;
! 	    nregs &= 0xf;
! 	    firstreg = code->dst.reg;
! 	    firstreg &= 0xf;
  	    for (i = firstreg; i >= firstreg - nregs; i--)
  	      {
  		h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
  		h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
  	      }
  	  }
! 	  goto next;
  
  	case O (O_DAA, SB):
  	  /* Decimal Adjust Addition.  This is for BCD arithmetic.  */
! 	  res = GET_B_REG (code->src.reg);
  	  if (!c && (0 <= (res >>  4) && (res >>  4) <= 9) && 
  	      !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
  	    res = res;		/* Value added == 0.  */
--- 4252,4284 ----
  	  goto next;
  
  	case O (O_LDM, SL):			/* ldm,  load from memory */
+ 	case O (O_RTEL, SN):			/* rte/l, ldm plus rte */
+ 	case O (O_RTSL, SN):			/* rts/l, ldm plus rts */
  	  {
  	    int nregs, firstreg, i;
  
! 	    nregs = ((GET_MEMORY_B (pc + 1) >> 4) & 0xf);
! 	    firstreg = code->dst.reg & 0xf;
  	    for (i = firstreg; i >= firstreg - nregs; i--)
  	      {
  		h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
  		h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
  	      }
  	  }
! 	  switch (code->opcode) {
! 	  case O (O_RTEL, SN):
! 	    goto rte;
! 	  case O (O_RTSL, SN):
! 	    goto rts;
! 	  case O (O_LDM, SL):
! 	    goto next;
! 	  default:
! 	    goto illegal;
! 	  }
  
  	case O (O_DAA, SB):
  	  /* Decimal Adjust Addition.  This is for BCD arithmetic.  */
! 	  res = GET_B_REG (code->src.reg);	/* FIXME fetch? */
  	  if (!c && (0 <= (res >>  4) && (res >>  4) <= 9) && 
  	      !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
  	    res = res;		/* Value added == 0.  */
*************** sim_resume (SIM_DESC sd, int step, int s
*** 4274,4288 ****
  	  code->dst.type == X (OP_CCR, SW))
  	{
  	  h8_set_ccr (sd, res);
! 	  /* Get Status Register (flags).  */
! 	  c = (h8_get_ccr (sd) >> 0) & 1;
! 	  v = (h8_get_ccr (sd) >> 1) & 1;
! 	  nz = !((h8_get_ccr (sd) >> 2) & 1);
! 	  n = (h8_get_ccr (sd) >> 3) & 1;
! 	  u = (h8_get_ccr (sd) >> 4) & 1;
! 	  h = (h8_get_ccr (sd) >> 5) & 1;
! 	  ui = ((h8_get_ccr (sd) >> 6) & 1);
! 	  intMaskBit = (h8_get_ccr (sd) >> 7) & 1;
  	}
        else if (h8300smode &&
  	       (code->dst.type == X (OP_EXR, SB) ||
--- 4344,4350 ----
  	  code->dst.type == X (OP_CCR, SW))
  	{
  	  h8_set_ccr (sd, res);
! 	  GETSR (sd);
  	}
        else if (h8300smode &&
  	       (code->dst.type == X (OP_EXR, SB) ||

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