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[patch] sim/mips/mips.igen: fix some trivial bugs


The following patch fixes some trivial bugs (and makes one or two
trivial additions) to the mips igen file.

Apply in sim/mips, over my previous patch.

2000-12-05  Chris Demetriou  cgd@sibyte.com

	* mips.igen (ADDI): Print immediate value.
	(BREAK): Print code.
	(DADDIU, DSRAV, DSRLV): Print correct instruction name.
	(SLL): Print "nop" specially, and don't run the code
	that does the shift for the "nop" case.

The only thing that I see as being possibly controversial is the
latter.  I think it's pretty smart to make that change.  (In the nop
case, when tracing, for instance, it's really silly to get output.)


chris
============
diff -rc ../src.P00/sim/mips/mips.igen ./sim/mips/mips.igen
*** ../src.P00/sim/mips/mips.igen	Tue Dec  5 16:30:53 2000
--- ./sim/mips/mips.igen	Tue Dec  5 16:44:01 2000
***************
*** 264,270 ****
  
  
  001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
! "addi r<RT>, r<RS>, IMMEDIATE"
  *mipsI:
  *mipsII:
  *mipsIII:
--- 264,270 ----
  
  
  001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
! "addi r<RT>, r<RS>, <IMMEDIATE>"
  *mipsI:
  *mipsII:
  *mipsIII:
***************
*** 726,732 ****
  
  
  000000,20.CODE,001101:SPECIAL:32::BREAK
! "break"
  *mipsI:
  *mipsII:
  *mipsIII:
--- 726,732 ----
  
  
  000000,20.CODE,001101:SPECIAL:32::BREAK
! "break <CODE>"
  *mipsI:
  *mipsII:
  *mipsIII:
***************
*** 807,813 ****
  }
  
  011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
! "daddu r<RT>, r<RS>, <IMMEDIATE>"
  *mipsIII:
  *mipsIV:
  *vr4100:
--- 807,813 ----
  }
  
  011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
! "daddiu r<RT>, r<RS>, <IMMEDIATE>"
  *mipsIII:
  *mipsIV:
  *vr4100:
***************
*** 1181,1187 ****
  }
  
  000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
! "dsra32 r<RT>, r<RD>, r<RS>"
  *mipsIII:
  *mipsIV:
  *vr4100:
--- 1181,1187 ----
  }
  
  000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
! "dsrav r<RT>, r<RD>, r<RS>"
  *mipsIII:
  *mipsIV:
  *vr4100:
***************
*** 1228,1234 ****
  
  
  000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
! "dsrl32 r<RD>, r<RT>, r<RS>"
  *mipsIII:
  *mipsIV:
  *vr4100:
--- 1228,1234 ----
  
  
  000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
! "dsrlv r<RD>, r<RT>, r<RS>"
  *mipsIII:
  *mipsIV:
  *vr4100:
***************
*** 2152,2157 ****
--- 2152,2158 ----
  }
  
  00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+ "nop":RD == 0 && RT == 0 && SHIFT == 0
  "sll r<RD>, r<RT>, <SHIFT>"
  *mipsI:
  *mipsII:
***************
*** 2161,2167 ****
  *vr5000:
  *r3900:
  {
!   do_sll (SD_, RT, RD, SHIFT);
  }
  
  
--- 2162,2169 ----
  *vr5000:
  *r3900:
  {
!   if (RD != 0 || RT != 0 || SHIFT != 0)   /* Skip encoding of NOP.  */
!     do_sll (SD_, RT, RD, SHIFT);
  }
  
  


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