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[binutils-gdb] Tidy up AArch64 simulator code.
- From: Nick Clifton <nickc at sourceware dot org>
- To: gdb-cvs at sourceware dot org
- Date: 29 Mar 2016 10:34:52 -0000
- Subject: [binutils-gdb] Tidy up AArch64 simulator code.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ef0d8ffc45aa32ed1e49051a344fa6c8cff583f4
commit ef0d8ffc45aa32ed1e49051a344fa6c8cff583f4
Author: Nick Clifton <nickc@redhat.com>
Date: Tue Mar 29 11:34:22 2016 +0100
Tidy up AArch64 simulator code.
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
Diff:
---
sim/aarch64/ChangeLog | 9 +
sim/aarch64/cpustate.c | 14 +-
sim/aarch64/decode.h | 44 -
sim/aarch64/simulator.c | 2815 +++++++++++++++++++++++------------------------
4 files changed, 1413 insertions(+), 1469 deletions(-)
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog
index 58ef3af..b9b7a2f 100644
--- a/sim/aarch64/ChangeLog
+++ b/sim/aarch64/ChangeLog
@@ -1,3 +1,12 @@
+2016-03-29 Nick Clifton <nickc@redhat.com>
+
+ * cpustate.c: Remove space after asterisk in function parameters.
+ * decode.h (greg): Delete unused function.
+ (vreg, shift, extension, scaling, writeback, condcode): Likewise.
+ * simulator.c: Use INSTR macro in more places.
+ (HALT_NYI): Use sim_io_eprintf in place of fprintf.
+ Remove extraneous whitespace.
+
2016-03-23 Nick Clifton <nickc@redhat.com>
* cpustate.c (aarch64_get_FP_half): New function. Read a vector
diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c
index 0656af5..4451b5d 100644
--- a/sim/aarch64/cpustate.c
+++ b/sim/aarch64/cpustate.c
@@ -470,25 +470,25 @@ aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
while (0)
void
-aarch64_set_vec_u64 (sim_cpu * cpu, VReg reg, unsigned element, uint64_t val)
+aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
{
SET_VEC_ELEMENT (reg, element, val, v, "%16lx");
}
void
-aarch64_set_vec_u32 (sim_cpu * cpu, VReg reg, unsigned element, uint32_t val)
+aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
{
SET_VEC_ELEMENT (reg, element, val, w, "%8x");
}
void
-aarch64_set_vec_u16 (sim_cpu * cpu, VReg reg, unsigned element, uint16_t val)
+aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
{
SET_VEC_ELEMENT (reg, element, val, h, "%4x");
}
void
-aarch64_set_vec_u8 (sim_cpu * cpu, VReg reg, unsigned element, uint8_t val)
+aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
{
SET_VEC_ELEMENT (reg, element, val, b, "%x");
}
@@ -573,19 +573,19 @@ aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
}
uint64_t
-aarch64_get_thread_id (sim_cpu * cpu)
+aarch64_get_thread_id (sim_cpu *cpu)
{
return cpu->tpidr;
}
uint32_t
-aarch64_get_FPCR (sim_cpu * cpu)
+aarch64_get_FPCR (sim_cpu *cpu)
{
return cpu->FPCR;
}
void
-aarch64_set_FPCR (sim_cpu * cpu, uint32_t val)
+aarch64_set_FPCR (sim_cpu *cpu, uint32_t val)
{
if (cpu->FPCR != val)
TRACE_REGISTER (cpu,
diff --git a/sim/aarch64/decode.h b/sim/aarch64/decode.h
index 49bfa9e..745b035 100644
--- a/sim/aarch64/decode.h
+++ b/sim/aarch64/decode.h
@@ -177,20 +177,6 @@ pickbits64 (uint64_t val, int hi, int lo)
return pick64 (val, hi, lo) >> lo;
}
-/* Decode registers, immediates and constants of various types. */
-
-static inline GReg
-greg (uint32_t val, int lo)
-{
- return (GReg) pickbits32 (val, lo + 4, lo);
-}
-
-static inline VReg
-vreg (uint32_t val, int lo)
-{
- return (VReg) pickbits32 (val, lo + 4, lo);
-}
-
static inline uint32_t
uimm (uint32_t val, int hi, int lo)
{
@@ -223,36 +209,6 @@ simm64 (uint64_t val, int hi, int lo)
return x.n >> (63 - hi + lo);
}
-static inline Shift
-shift (uint32_t val, int lo)
-{
- return (Shift) pickbits32 (val, lo + 1, lo);
-}
-
-static inline Extension
-extension (uint32_t val, int lo)
-{
- return (Extension) pickbits32 (val, lo + 2, lo);
-}
-
-static inline Scaling
-scaling (uint32_t val, int lo)
-{
- return (Scaling) pickbits32 (val, lo, lo);
-}
-
-static inline WriteBack
-writeback (uint32_t val, int lo)
-{
- return (WriteBack) pickbits32 (val, lo, lo);
-}
-
-static inline CondCode
-condcode (uint32_t val, int lo)
-{
- return (CondCode) pickbits32 (val, lo + 3, lo);
-}
-
/* Operation decode.
Bits [28,24] are the primary dispatch vector. */
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index a0231fd..1695174 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -39,6 +39,9 @@
#define IS_SET(_X) (TST (( _X )) ? 1 : 0)
#define IS_CLEAR(_X) (TST (( _X )) ? 0 : 1)
+/* Space saver macro. */
+#define INSTR(HIGH, LOW) uimm (aarch64_get_instr (cpu), (HIGH), (LOW))
+
#define HALT_UNALLOC \
do \
{ \
@@ -62,7 +65,7 @@
__LINE__, aarch64_get_PC (cpu)); \
if (! TRACE_ANY_P (cpu)) \
{ \
- fprintf (stderr, "SIM Error: Unimplemented instruction: "); \
+ sim_io_eprintf (CPU_STATE (cpu), "SIM Error: Unimplemented instruction: "); \
trace_disasm (CPU_STATE (cpu), cpu, aarch64_get_PC (cpu)); \
} \
sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu),\
@@ -73,14 +76,11 @@
#define NYI_assert(HI, LO, EXPECTED) \
do \
{ \
- if (uimm (aarch64_get_instr (cpu), (HI), (LO)) != (EXPECTED)) \
+ if (INSTR ((HI), (LO)) != (EXPECTED)) \
HALT_NYI; \
} \
while (0)
-/* Space saver macro. */
-#define INSTR(HIGH, LOW) uimm (aarch64_get_instr (cpu), (HIGH), (LOW))
-
/* Helper functions used by expandLogicalImmediate. */
/* for i = 1, ... N result<i-1> = 1 other bits are zero */
@@ -179,7 +179,7 @@ dexNotify (sim_cpu *cpu)
{
/* instr[14,0] == type : 0 ==> method entry, 1 ==> method reentry
2 ==> exit Java, 3 ==> start next bytecode. */
- uint32_t type = uimm (aarch64_get_instr (cpu), 14, 0);
+ uint32_t type = INSTR (14, 0);
TRACE_EVENTS (cpu, "Notify Insn encountered, type = 0x%x", type);
@@ -234,7 +234,7 @@ dexPseudo (sim_cpu *cpu)
sim_stopped, SIM_SIGTRAP);
}
- dispatch = uimm (aarch64_get_instr (cpu), 31, 15);
+ dispatch = INSTR (31, 15);
/* We do not handle callouts at the moment. */
if (dispatch == PSEUDO_CALLOUT || dispatch == PSEUDO_CALLOUTR)
@@ -262,8 +262,8 @@ dexPseudo (sim_cpu *cpu)
static void
ldur32 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_u32
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -274,8 +274,8 @@ ldur32 (sim_cpu *cpu, int32_t offset)
static void
ldur64 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_u64
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -286,8 +286,8 @@ ldur64 (sim_cpu *cpu, int32_t offset)
static void
ldurb32 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_u8
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -298,8 +298,8 @@ ldurb32 (sim_cpu *cpu, int32_t offset)
static void
ldursb32 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rt, NO_SP, (uint32_t) aarch64_get_mem_s8
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -310,8 +310,8 @@ ldursb32 (sim_cpu *cpu, int32_t offset)
static void
ldursb64 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_reg_s64 (cpu, rt, NO_SP, aarch64_get_mem_s8
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -322,8 +322,8 @@ ldursb64 (sim_cpu *cpu, int32_t offset)
static void
ldurh32 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP, aarch64_get_mem_u16
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -334,8 +334,8 @@ ldurh32 (sim_cpu *cpu, int32_t offset)
static void
ldursh32 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP, (uint32_t) aarch64_get_mem_s16
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -346,8 +346,8 @@ ldursh32 (sim_cpu *cpu, int32_t offset)
static void
ldursh64 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_reg_s64 (cpu, rt, NO_SP, aarch64_get_mem_s16
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -358,8 +358,8 @@ ldursh64 (sim_cpu *cpu, int32_t offset)
static void
ldursw (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP, (uint32_t) aarch64_get_mem_s32
(cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -373,8 +373,8 @@ ldursw (sim_cpu *cpu, int32_t offset)
static void
stur32 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_mem_u32 (cpu,
aarch64_get_reg_u64 (cpu, rn, SP_OK) + offset,
@@ -385,8 +385,8 @@ stur32 (sim_cpu *cpu, int32_t offset)
static void
stur64 (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_mem_u64 (cpu,
aarch64_get_reg_u64 (cpu, rn, SP_OK) + offset,
@@ -397,8 +397,8 @@ stur64 (sim_cpu *cpu, int32_t offset)
static void
sturb (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_mem_u8 (cpu,
aarch64_get_reg_u64 (cpu, rn, SP_OK) + offset,
@@ -409,8 +409,8 @@ sturb (sim_cpu *cpu, int32_t offset)
static void
sturh (sim_cpu *cpu, int32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_mem_u16 (cpu,
aarch64_get_reg_u64 (cpu, rn, SP_OK) + offset,
@@ -425,7 +425,7 @@ sturh (sim_cpu *cpu, int32_t offset)
static void
ldr32_pcrel (sim_cpu *cpu, int32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_mem_u32
@@ -436,7 +436,7 @@ ldr32_pcrel (sim_cpu *cpu, int32_t offset)
static void
ldr_pcrel (sim_cpu *cpu, int32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_mem_u64
@@ -447,7 +447,7 @@ ldr_pcrel (sim_cpu *cpu, int32_t offset)
static void
ldrsw_pcrel (sim_cpu *cpu, int32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_mem_s32
@@ -458,7 +458,7 @@ ldrsw_pcrel (sim_cpu *cpu, int32_t offset)
static void
fldrs_pcrel (sim_cpu *cpu, int32_t offset)
{
- unsigned int rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned int rd = INSTR (4, 0);
aarch64_set_vec_u32 (cpu, rd, 0,
aarch64_get_mem_u32
@@ -469,7 +469,7 @@ fldrs_pcrel (sim_cpu *cpu, int32_t offset)
static void
fldrd_pcrel (sim_cpu *cpu, int32_t offset)
{
- unsigned int st = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned int st = INSTR (4, 0);
aarch64_set_vec_u64 (cpu, st, 0,
aarch64_get_mem_u64
@@ -480,7 +480,7 @@ fldrd_pcrel (sim_cpu *cpu, int32_t offset)
static void
fldrq_pcrel (sim_cpu *cpu, int32_t offset)
{
- unsigned int st = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned int st = INSTR (4, 0);
uint64_t addr = aarch64_get_PC (cpu) + offset * 4;
FRegister a;
@@ -538,8 +538,8 @@ extend (uint32_t value, Extension extension)
static void
fldrs_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned st = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned st = INSTR (4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
if (wb != Post)
@@ -557,8 +557,8 @@ fldrs_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
fldrb_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned rn = INSTR (9, 5);
uint64_t addr = aarch64_get_reg_u64 (cpu, rn, SP_OK) + offset;
aarch64_set_vec_u8 (cpu, rd, 0, aarch64_get_mem_u32 (cpu, addr));
@@ -568,8 +568,8 @@ fldrb_abs (sim_cpu *cpu, uint32_t offset)
static void
fldrh_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned rn = INSTR (9, 5);
uint64_t addr = aarch64_get_reg_u64 (cpu, rn, SP_OK) + SCALE (offset, 16);
aarch64_set_vec_u16 (cpu, rd, 0, aarch64_get_mem_u16 (cpu, addr));
@@ -579,8 +579,8 @@ fldrh_abs (sim_cpu *cpu, uint32_t offset)
static void
fldrs_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned rn = INSTR (9, 5);
uint64_t addr = aarch64_get_reg_u64 (cpu, rn, SP_OK) + SCALE (offset, 32);
aarch64_set_vec_u32 (cpu, rd, 0, aarch64_get_mem_u32 (cpu, addr));
@@ -590,8 +590,8 @@ fldrs_abs (sim_cpu *cpu, uint32_t offset)
static void
fldrd_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned rn = INSTR (9, 5);
uint64_t addr = aarch64_get_reg_u64 (cpu, rn, SP_OK) + SCALE (offset, 64);
aarch64_set_vec_u64 (cpu, rd, 0, aarch64_get_mem_u64 (cpu, addr));
@@ -601,8 +601,8 @@ fldrd_abs (sim_cpu *cpu, uint32_t offset)
static void
fldrq_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned rn = INSTR (9, 5);
uint64_t addr = aarch64_get_reg_u64 (cpu, rn, SP_OK) + SCALE (offset, 128);
aarch64_set_vec_u64 (cpu, rd, 0, aarch64_get_mem_u64 (cpu, addr));
@@ -614,9 +614,9 @@ fldrq_abs (sim_cpu *cpu, uint32_t offset)
static void
fldrs_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned st = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned st = INSTR (4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
int64_t extended = extend (aarch64_get_reg_u32 (cpu, rm, NO_SP), extension);
uint64_t displacement = OPT_SCALE (extended, 32, scaling);
@@ -629,8 +629,8 @@ fldrs_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
fldrd_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned st = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned st = INSTR (4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
if (wb != Post)
@@ -649,7 +649,7 @@ fldrd_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
fldrd_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
+ unsigned rm = INSTR (20, 16);
int64_t extended = extend (aarch64_get_reg_u32 (cpu, rm, NO_SP), extension);
uint64_t displacement = OPT_SCALE (extended, 64, scaling);
@@ -661,8 +661,8 @@ static void
fldrq_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
FRegister a;
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned st = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned st = INSTR (4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
if (wb != Post)
@@ -682,7 +682,7 @@ fldrq_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
fldrq_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
+ unsigned rm = INSTR (20, 16);
int64_t extended = extend (aarch64_get_reg_u32 (cpu, rm, NO_SP), extension);
uint64_t displacement = OPT_SCALE (extended, 128, scaling);
@@ -717,8 +717,8 @@ fldrq_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldr32_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_u32
@@ -730,8 +730,8 @@ ldr32_abs (sim_cpu *cpu, uint32_t offset)
static void
ldr32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -756,9 +756,9 @@ ldr32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldr32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -773,8 +773,8 @@ ldr32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldr_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_u64
@@ -786,8 +786,8 @@ ldr_abs (sim_cpu *cpu, uint32_t offset)
static void
ldr_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -812,9 +812,9 @@ ldr_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldr_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -829,8 +829,8 @@ ldr_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldrb32_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be
there is no scaling required for a byte load. */
@@ -843,8 +843,8 @@ ldrb32_abs (sim_cpu *cpu, uint32_t offset)
static void
ldrb32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -869,9 +869,9 @@ ldrb32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldrb32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -888,8 +888,8 @@ ldrb32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldrsb_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -921,9 +921,9 @@ ldrsb_abs (sim_cpu *cpu, uint32_t offset)
static void
ldrsb_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -938,8 +938,8 @@ ldrsb_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldrh32_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_u16
@@ -952,8 +952,8 @@ ldrh32_abs (sim_cpu *cpu, uint32_t offset)
static void
ldrh32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -978,9 +978,9 @@ ldrh32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldrh32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -995,8 +995,8 @@ ldrh32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldrsh32_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_reg_u64 (cpu, rt, NO_SP, (uint32_t) aarch64_get_mem_s16
@@ -1010,8 +1010,8 @@ ldrsh32_abs (sim_cpu *cpu, uint32_t offset)
static void
ldrsh32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1037,9 +1037,9 @@ ldrsh32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldrsh32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -1055,8 +1055,8 @@ ldrsh32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldrsh_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_reg_u64 (cpu, rt, NO_SP, aarch64_get_mem_s16
@@ -1069,8 +1069,8 @@ ldrsh_abs (sim_cpu *cpu, uint32_t offset)
static void
ldrsh64_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1095,9 +1095,9 @@ ldrsh64_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldrsh_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -1112,8 +1112,8 @@ ldrsh_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
ldrsw_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
return aarch64_set_reg_s64 (cpu, rt, NO_SP, aarch64_get_mem_s32
@@ -1126,8 +1126,8 @@ ldrsw_abs (sim_cpu *cpu, uint32_t offset)
static void
ldrsw_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1152,9 +1152,9 @@ ldrsw_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
ldrsw_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -1172,8 +1172,8 @@ ldrsw_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
str32_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_mem_u32 (cpu, (aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -1185,8 +1185,8 @@ str32_abs (sim_cpu *cpu, uint32_t offset)
static void
str32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1210,9 +1210,9 @@ str32_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
str32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
int64_t extended = extend (aarch64_get_reg_u32 (cpu, rm, NO_SP), extension);
@@ -1226,8 +1226,8 @@ str32_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
str_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
aarch64_set_mem_u64 (cpu,
aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -1239,8 +1239,8 @@ str_abs (sim_cpu *cpu, uint32_t offset)
static void
str_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1265,9 +1265,9 @@ str_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
str_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -1283,8 +1283,8 @@ str_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
strb_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be.
There is no scaling required for a byte load. */
@@ -1297,8 +1297,8 @@ strb_abs (sim_cpu *cpu, uint32_t offset)
static void
strb_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1323,9 +1323,9 @@ strb_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
strb_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -1341,8 +1341,8 @@ strb_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
static void
strh_abs (sim_cpu *cpu, uint32_t offset)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* The target register may not be SP but the source may be. */
aarch64_set_mem_u16 (cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -1354,8 +1354,8 @@ strh_abs (sim_cpu *cpu, uint32_t offset)
static void
strh_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address;
if (rn == rt && wb != NoWriteBack)
@@ -1380,9 +1380,9 @@ strh_wb (sim_cpu *cpu, int32_t offset, WriteBack wb)
static void
strh_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
/* rn may reference SP, rm and rt must reference ZR */
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
@@ -1404,7 +1404,7 @@ prfm_abs (sim_cpu *cpu, uint32_t offset)
10010 ==> PSTL2KEEP, 10001 ==> PSTL2STRM,
10100 ==> PSTL3KEEP, 10101 ==> PSTL3STRM,
ow ==> UNALLOC
- PrfOp prfop = prfop (aarch64_get_instr (cpu), 4, 0);
+ PrfOp prfop = prfop (instr, 4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK)
+ SCALE (offset, 64). */
@@ -1423,7 +1423,7 @@ prfm_scale_ext (sim_cpu *cpu, Scaling scaling, Extension extension)
10100 ==> PSTL3KEEP, 10101 ==> PSTL3STRM,
ow ==> UNALLOC
rn may reference SP, rm may only reference ZR
- PrfOp prfop = prfop (aarch64_get_instr (cpu), 4, 0);
+ PrfOp prfop = prfop (instr, 4, 0);
uint64_t base = aarch64_get_reg_u64 (cpu, rn, SP_OK);
int64_t extended = extend (aarch64_get_reg_u32 (cpu, rm, NO_SP),
extension);
@@ -1444,7 +1444,7 @@ prfm_pcrel (sim_cpu *cpu, int32_t offset)
10010 ==> PSTL2KEEP, 10001 ==> PSTL2STRM,
10100 ==> PSTL3KEEP, 10101 ==> PSTL3STRM,
ow ==> UNALLOC
- PrfOp prfop = prfop (aarch64_get_instr (cpu), 4, 0);
+ PrfOp prfop = prfop (instr, 4, 0);
uint64_t address = aarch64_get_PC (cpu) + offset. */
/* TODO : implement this */
@@ -1455,12 +1455,12 @@ prfm_pcrel (sim_cpu *cpu, int32_t offset)
static void
ldxr (sim_cpu *cpu)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
- int size = uimm (aarch64_get_instr (cpu), 31, 30);
- /* int ordered = uimm (aarch64_get_instr (cpu), 15, 15); */
- /* int exclusive = ! uimm (aarch64_get_instr (cpu), 23, 23); */
+ int size = INSTR (31, 30);
+ /* int ordered = INSTR (15, 15); */
+ /* int exclusive = ! INSTR (23, 23); */
switch (size)
{
@@ -1482,11 +1482,11 @@ ldxr (sim_cpu *cpu)
static void
stxr (sim_cpu *cpu)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned rs = uimm (aarch64_get_instr (cpu), 20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rt = INSTR (4, 0);
+ unsigned rs = INSTR (20, 16);
uint64_t address = aarch64_get_reg_u64 (cpu, rn, SP_OK);
- int size = uimm (aarch64_get_instr (cpu), 31, 30);
+ int size = INSTR (31, 30);
uint64_t data = aarch64_get_reg_u64 (cpu, rt, NO_SP);
switch (size)
@@ -1512,9 +1512,9 @@ dexLoadLiteral (sim_cpu *cpu)
instr[26] ==> V : 0 ==> GReg, 1 ==> FReg
instr[23, 5] == simm19 */
- /* unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0); */
- uint32_t dispatch = ( (uimm (aarch64_get_instr (cpu), 31, 30) << 1)
- | uimm (aarch64_get_instr (cpu), 26, 26));
+ /* unsigned rt = INSTR (4, 0); */
+ uint32_t dispatch = ( (INSTR (31, 30) << 1)
+ | INSTR (26, 26));
int32_t imm = simm32 (aarch64_get_instr (cpu), 23, 5);
switch (dispatch)
@@ -1544,8 +1544,8 @@ dexLoadLiteral (sim_cpu *cpu)
static void
add32 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u32 (cpu, rn, SP_OK) + aimm);
@@ -1555,8 +1555,8 @@ add32 (sim_cpu *cpu, uint32_t aimm)
static void
add64 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u64 (cpu, rn, SP_OK) + aimm);
@@ -1725,8 +1725,8 @@ set_flags_for_binop64 (sim_cpu *cpu, uint64_t result)
static void
adds32 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
/* TODO : do we need to worry about signs here? */
int32_t value1 = aarch64_get_reg_s32 (cpu, rn, SP_OK);
@@ -1738,8 +1738,8 @@ adds32 (sim_cpu *cpu, uint32_t aimm)
static void
adds64 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, SP_OK);
uint64_t value2 = aimm;
@@ -1751,8 +1751,8 @@ adds64 (sim_cpu *cpu, uint32_t aimm)
static void
sub32 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u32 (cpu, rn, SP_OK) - aimm);
@@ -1762,8 +1762,8 @@ sub32 (sim_cpu *cpu, uint32_t aimm)
static void
sub64 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u64 (cpu, rn, SP_OK) - aimm);
@@ -1773,8 +1773,8 @@ sub64 (sim_cpu *cpu, uint32_t aimm)
static void
subs32 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u64 (cpu, rn, SP_OK);
uint32_t value2 = aimm;
@@ -1786,8 +1786,8 @@ subs32 (sim_cpu *cpu, uint32_t aimm)
static void
subs64 (sim_cpu *cpu, uint32_t aimm)
{
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, SP_OK);
uint32_t value2 = aimm;
@@ -1857,9 +1857,9 @@ shifted64 (uint64_t value, Shift shift, uint32_t count)
static void
add32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u32 (cpu, rn, NO_SP)
@@ -1871,9 +1871,9 @@ add32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
add64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u64 (cpu, rn, NO_SP)
@@ -1885,9 +1885,9 @@ add64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
adds32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u32 (cpu, rn, NO_SP);
uint32_t value2 = shifted32 (aarch64_get_reg_u32 (cpu, rm, NO_SP),
@@ -1901,9 +1901,9 @@ adds32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
adds64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, NO_SP);
uint64_t value2 = shifted64 (aarch64_get_reg_u64 (cpu, rm, NO_SP),
@@ -1917,9 +1917,9 @@ adds64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
sub32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u32 (cpu, rn, NO_SP)
@@ -1931,9 +1931,9 @@ sub32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
sub64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u64 (cpu, rn, NO_SP)
@@ -1945,9 +1945,9 @@ sub64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
subs32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u32 (cpu, rn, NO_SP);
uint32_t value2 = shifted32 (aarch64_get_reg_u32 (cpu, rm, NO_SP),
@@ -1961,9 +1961,9 @@ subs32_shift (sim_cpu *cpu, Shift shift, uint32_t count)
static void
subs64_shift (sim_cpu *cpu, Shift shift, uint32_t count)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, NO_SP);
uint64_t value2 = shifted64 (aarch64_get_reg_u64 (cpu, rm, NO_SP),
@@ -2025,9 +2025,9 @@ extreg64 (sim_cpu *cpu, unsigned int lo, Extension extension)
static void
add32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u32 (cpu, rn, SP_OK)
@@ -2039,9 +2039,9 @@ add32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
add64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -2052,9 +2052,9 @@ add64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
adds32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u32 (cpu, rn, SP_OK);
uint32_t value2 = extreg32 (cpu, rm, extension) << shift;
@@ -2068,9 +2068,9 @@ adds32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
adds64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, SP_OK);
uint64_t value2 = extreg64 (cpu, rm, extension) << shift;
@@ -2083,9 +2083,9 @@ adds64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
sub32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u32 (cpu, rn, SP_OK)
@@ -2097,9 +2097,9 @@ sub32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
sub64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, SP_OK,
aarch64_get_reg_u64 (cpu, rn, SP_OK)
@@ -2110,9 +2110,9 @@ sub64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
subs32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u32 (cpu, rn, SP_OK);
uint32_t value2 = extreg32 (cpu, rm, extension) << shift;
@@ -2126,9 +2126,9 @@ subs32_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
static void
subs64_ext (sim_cpu *cpu, Extension extension, uint32_t shift)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, SP_OK);
uint64_t value2 = extreg64 (cpu, rm, extension) << shift;
@@ -2150,9 +2150,9 @@ dexAddSubtractImmediate (sim_cpu *cpu)
instr[4,0] = Rd */
/* N.B. the shift is applied at decode before calling the add/sub routine. */
- uint32_t shift = uimm (aarch64_get_instr (cpu), 23, 22);
- uint32_t imm = uimm (aarch64_get_instr (cpu), 21, 10);
- uint32_t dispatch = uimm (aarch64_get_instr (cpu), 31, 29);
+ uint32_t shift = INSTR (23, 22);
+ uint32_t imm = INSTR (21, 10);
+ uint32_t dispatch = INSTR (31, 29);
NYI_assert (28, 24, 0x11);
@@ -2188,25 +2188,24 @@ dexAddSubtractShiftedRegister (sim_cpu *cpu)
instr[9,5] = Rn
instr[4,0] = Rd */
- uint32_t size = uimm (aarch64_get_instr (cpu), 31, 31);
- /* 32 bit operations must have count[5] = 0
- or else we have an UNALLOC. */
- uint32_t count = uimm (aarch64_get_instr (cpu), 15, 10);
- /* Shift encoded as ROR is unallocated. */
- Shift shiftType = shift (aarch64_get_instr (cpu), 22);
- /* Dispatch on size:op i.e aarch64_get_instr (cpu)[31,29]. */
- uint32_t dispatch = uimm (aarch64_get_instr (cpu), 31, 29);
+ uint32_t size = INSTR (31, 31);
+ uint32_t count = INSTR (15, 10);
+ Shift shiftType = INSTR (23, 22);
NYI_assert (28, 24, 0x0B);
NYI_assert (21, 21, 0);
+ /* Shift encoded as ROR is unallocated. */
if (shiftType == ROR)
HALT_UNALLOC;
- if (!size && uimm (count, 5, 5))
+ /* 32 bit operations must have count[5] = 0
+ or else we have an UNALLOC. */
+ if (size == 0 && uimm (count, 5, 5))
HALT_UNALLOC;
- switch (dispatch)
+ /* Dispatch on size:op i.e instr [31,29]. */
+ switch (INSTR (31, 29))
{
case 0: add32_shift (cpu, shiftType, count); break;
case 1: adds32_shift (cpu, shiftType, count); break;
@@ -2237,10 +2236,8 @@ dexAddSubtractExtendedRegister (sim_cpu *cpu)
instr[9,5] = Rn
instr[4,0] = Rd */
- Extension extensionType = extension (aarch64_get_instr (cpu), 13);
- uint32_t shift = uimm (aarch64_get_instr (cpu), 12, 10);
- /* dispatch on size:op:set? i.e aarch64_get_instr (cpu)[31,29] */
- uint32_t dispatch = uimm (aarch64_get_instr (cpu), 31, 29);
+ Extension extensionType = INSTR (15, 13);
+ uint32_t shift = INSTR (12, 10);
NYI_assert (28, 24, 0x0B);
NYI_assert (21, 21, 1);
@@ -2249,7 +2246,8 @@ dexAddSubtractExtendedRegister (sim_cpu *cpu)
if (shift > 4)
HALT_UNALLOC;
- switch (dispatch)
+ /* Dispatch on size:op:set?. */
+ switch (INSTR (31, 29))
{
case 0: add32_ext (cpu, extensionType, shift); break;
case 1: adds32_ext (cpu, extensionType, shift); break;
@@ -2271,9 +2269,9 @@ dexAddSubtractExtendedRegister (sim_cpu *cpu)
static void
adc32 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u32 (cpu, rn, NO_SP)
@@ -2285,9 +2283,9 @@ adc32 (sim_cpu *cpu)
static void
adc64 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u64 (cpu, rn, NO_SP)
@@ -2299,9 +2297,9 @@ adc64 (sim_cpu *cpu)
static void
adcs32 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u32 (cpu, rn, NO_SP);
uint32_t value2 = aarch64_get_reg_u32 (cpu, rm, NO_SP);
@@ -2315,9 +2313,9 @@ adcs32 (sim_cpu *cpu)
static void
adcs64 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, NO_SP);
uint64_t value2 = aarch64_get_reg_u64 (cpu, rm, NO_SP);
@@ -2331,9 +2329,9 @@ adcs64 (sim_cpu *cpu)
static void
sbc32 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5); /* ngc iff rn == 31. */
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5); /* ngc iff rn == 31. */
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u32 (cpu, rn, NO_SP)
@@ -2345,9 +2343,9 @@ sbc32 (sim_cpu *cpu)
static void
sbc64 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_reg_u64 (cpu, rn, NO_SP)
@@ -2359,9 +2357,9 @@ sbc64 (sim_cpu *cpu)
static void
sbcs32 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint32_t value1 = aarch64_get_reg_u32 (cpu, rn, NO_SP);
uint32_t value2 = aarch64_get_reg_u32 (cpu, rm, NO_SP);
@@ -2376,9 +2374,9 @@ sbcs32 (sim_cpu *cpu)
static void
sbcs64 (sim_cpu *cpu)
{
- unsigned rm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rm = INSTR (20, 16);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
uint64_t value1 = aarch64_get_reg_u64 (cpu, rn, NO_SP);
uint64_t value2 = aarch64_get_reg_u64 (cpu, rm, NO_SP);
@@ -2401,16 +2399,15 @@ dexAddSubtractWithCarry (sim_cpu *cpu)
instr[9,5] = Rn
instr[4,0] = Rd */
- uint32_t op2 = uimm (aarch64_get_instr (cpu), 15, 10);
- /* Dispatch on size:op:set? i.e aarch64_get_instr (cpu)[31,29] */
- uint32_t dispatch = uimm (aarch64_get_instr (cpu), 31, 29);
+ uint32_t op2 = INSTR (15, 10);
NYI_assert (28, 21, 0xD0);
if (op2 != 0)
HALT_UNALLOC;
- switch (dispatch)
+ /* Dispatch on size:op:set?. */
+ switch (INSTR (31, 29))
{
case 0: adc32 (cpu); break;
case 1: adcs32 (cpu); break;
@@ -2480,19 +2477,19 @@ CondCompare (sim_cpu *cpu) /* aka: ccmp and ccmn */
NYI_assert (10, 10, 0);
NYI_assert (4, 4, 0);
- if (! testConditionCode (cpu, uimm (aarch64_get_instr (cpu), 15, 12)))
+ if (! testConditionCode (cpu, INSTR (15, 12)))
{
- aarch64_set_CPSR (cpu, uimm (aarch64_get_instr (cpu), 3, 0));
+ aarch64_set_CPSR (cpu, INSTR (3, 0));
return;
}
- negate = uimm (aarch64_get_instr (cpu), 30, 30) ? 1 : -1;
- rm = uimm (aarch64_get_instr (cpu), 20, 16);
- rn = uimm (aarch64_get_instr (cpu), 9, 5);
+ negate = INSTR (30, 30) ? 1 : -1;
+ rm = INSTR (20, 16);
+ rn = INSTR ( 9, 5);
- if (uimm (aarch64_get_instr (cpu), 31, 31))
+ if (INSTR (31, 31))
{
- if (uimm (aarch64_get_instr (cpu), 11, 11))
+ if (INSTR (11, 11))
set_flags_for_sub64 (cpu, aarch64_get_reg_u64 (cpu, rn, SP_OK),
negate * (uint64_t) rm);
else
@@ -2501,7 +2498,7 @@ CondCompare (sim_cpu *cpu) /* aka: ccmp and ccmn */
}
else
{
- if (uimm (aarch64_get_instr (cpu), 11, 11))
+ if (INSTR (11, 11))
set_flags_for_sub32 (cpu, aarch64_get_reg_u32 (cpu, rn, SP_OK),
negate * rm);
else
@@ -2523,16 +2520,16 @@ do_vec_MOV_whole_vector (sim_cpu *cpu)
instr[9,5] = Vs
instr[4,0] = Vd */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vs = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
NYI_assert (29, 21, 0x075);
NYI_assert (15, 10, 0x07);
- if (uimm (aarch64_get_instr (cpu), 20, 16) != vs)
+ if (INSTR (20, 16) != vs)
HALT_NYI;
- if (uimm (aarch64_get_instr (cpu), 30, 30))
+ if (INSTR (30, 30))
aarch64_set_vec_u64 (cpu, vd, 1, aarch64_get_vec_u64 (cpu, vs, 1));
aarch64_set_vec_u64 (cpu, vd, 0, aarch64_get_vec_u64 (cpu, vs, 0));
@@ -2549,13 +2546,13 @@ do_vec_MOV_into_scalar (sim_cpu *cpu)
instr[9,5] = V source
instr[4,0] = R dest */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vs = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
NYI_assert (29, 21, 0x070);
NYI_assert (17, 10, 0x0F);
- switch (uimm (aarch64_get_instr (cpu), 20, 18))
+ switch (INSTR (20, 18))
{
case 0x2:
aarch64_set_reg_u64 (cpu, rd, NO_SP, aarch64_get_vec_u64 (cpu, vs, 0));
@@ -2570,7 +2567,7 @@ do_vec_MOV_into_scalar (sim_cpu *cpu)
case 0x5:
case 0x7:
aarch64_set_reg_u64 (cpu, rd, NO_SP, aarch64_get_vec_u32
- (cpu, vs, uimm (aarch64_get_instr (cpu), 20, 19)));
+ (cpu, vs, INSTR (20, 19)));
break;
default:
@@ -2588,33 +2585,33 @@ do_vec_INS (sim_cpu *cpu)
instr[4,0] = V dest */
int index;
- unsigned rs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned rs = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
NYI_assert (31, 21, 0x270);
NYI_assert (15, 10, 0x07);
- if (uimm (aarch64_get_instr (cpu), 16, 16))
+ if (INSTR (16, 16))
{
- index = uimm (aarch64_get_instr (cpu), 20, 17);
+ index = INSTR (20, 17);
aarch64_set_vec_u8 (cpu, vd, index,
aarch64_get_reg_u8 (cpu, rs, NO_SP));
}
- else if (uimm (aarch64_get_instr (cpu), 17, 17))
+ else if (INSTR (17, 17))
{
- index = uimm (aarch64_get_instr (cpu), 20, 18);
+ index = INSTR (20, 18);
aarch64_set_vec_u16 (cpu, vd, index,
aarch64_get_reg_u16 (cpu, rs, NO_SP));
}
- else if (uimm (aarch64_get_instr (cpu), 18, 18))
+ else if (INSTR (18, 18))
{
- index = uimm (aarch64_get_instr (cpu), 20, 19);
+ index = INSTR (20, 19);
aarch64_set_vec_u32 (cpu, vd, index,
aarch64_get_reg_u32 (cpu, rs, NO_SP));
}
- else if (uimm (aarch64_get_instr (cpu), 19, 19))
+ else if (INSTR (19, 19))
{
- index = uimm (aarch64_get_instr (cpu), 20, 20);
+ index = INSTR (20, 20);
aarch64_set_vec_u64 (cpu, vd, index,
aarch64_get_reg_u64 (cpu, rs, NO_SP));
}
@@ -2633,44 +2630,44 @@ do_vec_DUP_vector_into_vector (sim_cpu *cpu)
instr[9,5] = V source
instr[4,0] = V dest. */
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned vs = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
int i, index;
NYI_assert (29, 21, 0x070);
NYI_assert (15, 10, 0x01);
- if (uimm (aarch64_get_instr (cpu), 16, 16))
+ if (INSTR (16, 16))
{
- index = uimm (aarch64_get_instr (cpu), 20, 17);
+ index = INSTR (20, 17);
for (i = 0; i < (full ? 16 : 8); i++)
aarch64_set_vec_u8 (cpu, vd, i, aarch64_get_vec_u8 (cpu, vs, index));
}
- else if (uimm (aarch64_get_instr (cpu), 17, 17))
+ else if (INSTR (17, 17))
{
- index = uimm (aarch64_get_instr (cpu), 20, 18);
+ index = INSTR (20, 18);
for (i = 0; i < (full ? 8 : 4); i++)
aarch64_set_vec_u16 (cpu, vd, i, aarch64_get_vec_u16 (cpu, vs, index));
}
- else if (uimm (aarch64_get_instr (cpu), 18, 18))
+ else if (INSTR (18, 18))
{
- index = uimm (aarch64_get_instr (cpu), 20, 19);
+ index = INSTR (20, 19);
for (i = 0; i < (full ? 4 : 2); i++)
aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vs, index));
}
else
{
- if (uimm (aarch64_get_instr (cpu), 19, 19) == 0)
+ if (INSTR (19, 19) == 0)
HALT_UNALLOC;
if (! full)
HALT_UNALLOC;
- index = uimm (aarch64_get_instr (cpu), 20, 20);
+ index = INSTR (20, 20);
for (i = 0; i < 2; i++)
aarch64_set_vec_u64 (cpu, vd, i, aarch64_get_vec_u64 (cpu, vs, index));
@@ -2690,11 +2687,11 @@ do_vec_TBL (sim_cpu *cpu)
instr[9,5] = V start
instr[4,0] = V dest */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- int len = uimm (aarch64_get_instr (cpu), 14, 13) + 1;
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ int full = INSTR (30, 30);
+ int len = INSTR (14, 13) + 1;
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
NYI_assert (29, 21, 0x070);
@@ -2735,17 +2732,17 @@ do_vec_TRN (sim_cpu *cpu)
instr[9,5] = V source
instr[4,0] = V dest. */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- int second = uimm (aarch64_get_instr (cpu), 14, 14);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ int full = INSTR (30, 30);
+ int second = INSTR (14, 14);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
NYI_assert (29, 24, 0x0E);
NYI_assert (13, 10, 0xA);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 8 : 4); i++)
@@ -2808,14 +2805,14 @@ do_vec_DUP_scalar_into_vector (sim_cpu *cpu)
instr[4,0] = V dest. */
unsigned i;
- unsigned Vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned Rs = uimm (aarch64_get_instr (cpu), 9, 5);
- int both = uimm (aarch64_get_instr (cpu), 30, 30);
+ unsigned Vd = INSTR (4, 0);
+ unsigned Rs = INSTR (9, 5);
+ int both = INSTR (30, 30);
NYI_assert (29, 20, 0x0E0);
NYI_assert (15, 10, 0x03);
- switch (uimm (aarch64_get_instr (cpu), 19, 16))
+ switch (INSTR (19, 16))
{
case 1:
for (i = 0; i < (both ? 16 : 8); i++)
@@ -2859,12 +2856,12 @@ do_vec_UZP (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd. */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- int upper = uimm (aarch64_get_instr (cpu), 14, 14);
+ int full = INSTR (30, 30);
+ int upper = INSTR (14, 14);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
uint64_t val_m1 = aarch64_get_vec_u64 (cpu, vm, 0);
uint64_t val_m2 = aarch64_get_vec_u64 (cpu, vm, 1);
@@ -2883,7 +2880,7 @@ do_vec_UZP (sim_cpu *cpu)
NYI_assert (15, 15, 0);
NYI_assert (13, 10, 6);
- switch (uimm (aarch64_get_instr (cpu), 23, 23))
+ switch (INSTR (23, 23))
{
case 0:
for (i = 0; i < 8; i++)
@@ -2931,12 +2928,12 @@ do_vec_ZIP (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd. */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- int upper = uimm (aarch64_get_instr (cpu), 14, 14);
+ int full = INSTR (30, 30);
+ int upper = INSTR (14, 14);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
uint64_t val_m1 = aarch64_get_vec_u64 (cpu, vm, 0);
uint64_t val_m2 = aarch64_get_vec_u64 (cpu, vm, 1);
@@ -2954,7 +2951,7 @@ do_vec_ZIP (sim_cpu *cpu)
NYI_assert (15, 15, 0);
NYI_assert (13, 10, 0xE);
- switch (uimm (aarch64_get_instr (cpu), 23, 23))
+ switch (INSTR (23, 23))
{
case 0:
val1 =
@@ -3106,22 +3103,22 @@ do_vec_MOV_immediate (sim_cpu *cpu)
instr[9,5] = low 5-bits of uimm8
instr[4,0] = Vd. */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned val = uimm (aarch64_get_instr (cpu), 18, 16) << 5
- | uimm (aarch64_get_instr (cpu), 9, 5);
+ int full = INSTR (30, 30);
+ unsigned vd = INSTR (4, 0);
+ unsigned val = INSTR (18, 16) << 5
+ | INSTR (9, 5);
unsigned i;
NYI_assert (29, 19, 0x1E0);
NYI_assert (11, 10, 1);
- switch (uimm (aarch64_get_instr (cpu), 15, 12))
+ switch (INSTR (15, 12))
{
case 0x0: /* 32-bit, no shift. */
case 0x2: /* 32-bit, shift by 8. */
case 0x4: /* 32-bit, shift by 16. */
case 0x6: /* 32-bit, shift by 24. */
- val <<= (8 * uimm (aarch64_get_instr (cpu), 14, 13));
+ val <<= (8 * INSTR (14, 13));
for (i = 0; i < (full ? 4 : 2); i++)
aarch64_set_vec_u32 (cpu, vd, i, val);
break;
@@ -3174,22 +3171,22 @@ do_vec_MVNI (sim_cpu *cpu)
instr[9,5] = low 5-bits of uimm8
instr[4,0] = Vd. */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned val = uimm (aarch64_get_instr (cpu), 18, 16) << 5
- | uimm (aarch64_get_instr (cpu), 9, 5);
+ int full = INSTR (30, 30);
+ unsigned vd = INSTR (4, 0);
+ unsigned val = INSTR (18, 16) << 5
+ | INSTR (9, 5);
unsigned i;
NYI_assert (29, 19, 0x5E0);
NYI_assert (11, 10, 1);
- switch (uimm (aarch64_get_instr (cpu), 15, 12))
+ switch (INSTR (15, 12))
{
case 0x0: /* 32-bit, no shift. */
case 0x2: /* 32-bit, shift by 8. */
case 0x4: /* 32-bit, shift by 16. */
case 0x6: /* 32-bit, shift by 24. */
- val <<= (8 * uimm (aarch64_get_instr (cpu), 14, 13));
+ val <<= (8 * INSTR (14, 13));
val = ~ val;
for (i = 0; i < (full ? 4 : 2); i++)
aarch64_set_vec_u32 (cpu, vd, i, val);
@@ -3256,15 +3253,15 @@ do_vec_ABS (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
unsigned i;
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 10, 0x82E);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -3305,16 +3302,16 @@ do_vec_ADDV (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Rd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
unsigned i;
uint64_t val = 0;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 10, 0xC6E);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -3356,49 +3353,49 @@ do_vec_ins_2 (sim_cpu *cpu)
instr[4,0] = Vd. */
unsigned elem;
- unsigned vm = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
NYI_assert (31, 21, 0x270);
NYI_assert (17, 14, 0);
NYI_assert (12, 10, 7);
- if (uimm (aarch64_get_instr (cpu), 13, 13) == 1)
+ if (INSTR (13, 13) == 1)
{
- if (uimm (aarch64_get_instr (cpu), 18, 18) == 1)
+ if (INSTR (18, 18) == 1)
{
/* 32-bit moves. */
- elem = uimm (aarch64_get_instr (cpu), 20, 19);
+ elem = INSTR (20, 19);
aarch64_set_reg_u64 (cpu, vd, NO_SP,
aarch64_get_vec_u32 (cpu, vm, elem));
}
else
{
/* 64-bit moves. */
- if (uimm (aarch64_get_instr (cpu), 19, 19) != 1)
+ if (INSTR (19, 19) != 1)
HALT_NYI;
- elem = uimm (aarch64_get_instr (cpu), 20, 20);
+ elem = INSTR (20, 20);
aarch64_set_reg_u64 (cpu, vd, NO_SP,
aarch64_get_vec_u64 (cpu, vm, elem));
}
}
else
{
- if (uimm (aarch64_get_instr (cpu), 18, 18) == 1)
+ if (INSTR (18, 18) == 1)
{
/* 32-bit moves. */
- elem = uimm (aarch64_get_instr (cpu), 20, 19);
+ elem = INSTR (20, 19);
aarch64_set_vec_u32 (cpu, vd, elem,
aarch64_get_reg_u32 (cpu, vm, NO_SP));
}
else
{
/* 64-bit moves. */
- if (uimm (aarch64_get_instr (cpu), 19, 19) != 1)
+ if (INSTR (19, 19) != 1)
HALT_NYI;
- elem = uimm (aarch64_get_instr (cpu), 20, 20);
+ elem = INSTR (20, 20);
aarch64_set_vec_u64 (cpu, vd, elem,
aarch64_get_reg_u64 (cpu, vm, NO_SP));
}
@@ -3419,17 +3416,17 @@ do_vec_mull (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- int unsign = uimm (aarch64_get_instr (cpu), 29, 29);
- int bias = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ int unsign = INSTR (29, 29);
+ int bias = INSTR (30, 30);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR ( 9, 5);
+ unsigned vd = INSTR ( 4, 0);
unsigned i;
NYI_assert (28, 24, 0x0E);
NYI_assert (15, 10, 0x30);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
if (bias)
@@ -3497,19 +3494,19 @@ do_vec_fadd (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x35);
- if (uimm (aarch64_get_instr (cpu), 23, 23))
+ if (INSTR (23, 23))
{
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
if (! full)
HALT_NYI;
@@ -3529,7 +3526,7 @@ do_vec_fadd (sim_cpu *cpu)
}
else
{
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
if (! full)
HALT_NYI;
@@ -3562,17 +3559,17 @@ do_vec_add (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x21);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -3617,17 +3614,17 @@ do_vec_mul (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x27);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -3677,17 +3674,17 @@ do_vec_MLA (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x25);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -3786,29 +3783,29 @@ dminnm (double a, double b)
static void
do_vec_FminmaxNMP (sim_cpu *cpu)
{
- /* aarch64_get_instr (cpu)[31] = 0
- aarch64_get_instr (cpu)[30] = half (0)/full (1)
- aarch64_get_instr (cpu)[29,24] = 10 1110
- aarch64_get_instr (cpu)[23] = max(0)/min(1)
- aarch64_get_instr (cpu)[22] = float (0)/double (1)
- aarch64_get_instr (cpu)[21] = 1
- aarch64_get_instr (cpu)[20,16] = Vn
- aarch64_get_instr (cpu)[15,10] = 1100 01
- aarch64_get_instr (cpu)[9,5] = Vm
- aarch64_get_instr (cpu)[4.0] = Vd. */
-
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ /* instr [31] = 0
+ instr [30] = half (0)/full (1)
+ instr [29,24] = 10 1110
+ instr [23] = max(0)/min(1)
+ instr [22] = float (0)/double (1)
+ instr [21] = 1
+ instr [20,16] = Vn
+ instr [15,10] = 1100 01
+ instr [9,5] = Vm
+ instr [4.0] = Vd. */
+
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ int full = INSTR (30, 30);
NYI_assert (29, 24, 0x2E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x31);
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
- double (* fn)(double, double) = uimm (aarch64_get_instr (cpu), 23, 23)
+ double (* fn)(double, double) = INSTR (23, 23)
? dminnm : dmaxnm;
if (! full)
@@ -3822,7 +3819,7 @@ do_vec_FminmaxNMP (sim_cpu *cpu)
}
else
{
- float (* fn)(float, float) = uimm (aarch64_get_instr (cpu), 23, 23)
+ float (* fn)(float, float) = INSTR (23, 23)
? fminnm : fmaxnm;
aarch64_set_vec_float (cpu, vd, 0,
@@ -3854,11 +3851,11 @@ do_vec_AND (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 21, 0x071);
NYI_assert (15, 10, 0x07);
@@ -3880,11 +3877,11 @@ do_vec_BSL (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 21, 0x173);
NYI_assert (15, 10, 0x07);
@@ -3908,11 +3905,11 @@ do_vec_EOR (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 21, 0x171);
NYI_assert (15, 10, 0x07);
@@ -3936,11 +3933,11 @@ do_vec_bit (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned test_false = uimm (aarch64_get_instr (cpu), 22, 22);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned test_false = INSTR (22, 22);
unsigned i;
NYI_assert (29, 23, 0x5D);
@@ -3972,11 +3969,11 @@ do_vec_ORN (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 21, 0x077);
NYI_assert (15, 10, 0x07);
@@ -3998,11 +3995,11 @@ do_vec_ORR (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 21, 0x075);
NYI_assert (15, 10, 0x07);
@@ -4024,11 +4021,11 @@ do_vec_BIC (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 21, 0x073);
NYI_assert (15, 10, 0x07);
@@ -4050,15 +4047,15 @@ do_vec_XTN (sim_cpu *cpu)
instr[9,5] = Vs
instr[4,0] = Vd. */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned bias = uimm (aarch64_get_instr (cpu), 30, 30);
+ unsigned vs = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ unsigned bias = INSTR (30, 30);
unsigned i;
NYI_assert (29, 24, 0x0E);
NYI_assert (21, 10, 0x84A);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
if (bias)
@@ -4107,9 +4104,9 @@ do_vec_maxv (sim_cpu *cpu)
instr[9,5] = V source
instr[4.0] = R dest. */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
+ unsigned vs = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
unsigned i;
NYI_assert (28, 24, 0x0E);
@@ -4117,13 +4114,13 @@ do_vec_maxv (sim_cpu *cpu)
NYI_assert (20, 17, 8);
NYI_assert (15, 10, 0x2A);
- switch ((uimm (aarch64_get_instr (cpu), 29, 29) << 1)
- | uimm (aarch64_get_instr (cpu), 16, 16))
+ switch ((INSTR (29, 29) << 1)
+ | INSTR (16, 16))
{
case 0: /* SMAXV. */
{
int64_t smax;
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
smax = aarch64_get_vec_s8 (cpu, vs, 0);
@@ -4150,7 +4147,7 @@ do_vec_maxv (sim_cpu *cpu)
case 1: /* SMINV. */
{
int64_t smin;
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
smin = aarch64_get_vec_s8 (cpu, vs, 0);
@@ -4178,7 +4175,7 @@ do_vec_maxv (sim_cpu *cpu)
case 2: /* UMAXV. */
{
uint64_t umax;
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
umax = aarch64_get_vec_u8 (cpu, vs, 0);
@@ -4206,7 +4203,7 @@ do_vec_maxv (sim_cpu *cpu)
case 3: /* UMINV. */
{
uint64_t umin;
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
umin = aarch64_get_vec_u8 (cpu, vs, 0);
@@ -4244,8 +4241,8 @@ do_vec_fminmaxV (sim_cpu *cpu)
instr[9,5] = V source
instr[4.0] = R dest. */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vs = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
unsigned i;
float res = aarch64_get_vec_float (cpu, vs, 0);
@@ -4253,9 +4250,9 @@ do_vec_fminmaxV (sim_cpu *cpu)
NYI_assert (22, 14, 0x0C3);
NYI_assert (11, 10, 2);
- if (uimm (aarch64_get_instr (cpu), 23, 23))
+ if (INSTR (23, 23))
{
- switch (uimm (aarch64_get_instr (cpu), 13, 12))
+ switch (INSTR (13, 12))
{
case 0: /* FMNINNMV. */
for (i = 1; i < 4; i++)
@@ -4273,7 +4270,7 @@ do_vec_fminmaxV (sim_cpu *cpu)
}
else
{
- switch (uimm (aarch64_get_instr (cpu), 13, 12))
+ switch (INSTR (13, 12))
{
case 0: /* FMNAXNMV. */
for (i = 1; i < 4; i++)
@@ -4309,11 +4306,11 @@ do_vec_Fminmax (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned min = uimm (aarch64_get_instr (cpu), 23, 23);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned min = INSTR (23, 23);
unsigned i;
NYI_assert (29, 24, 0x0E);
@@ -4321,16 +4318,16 @@ do_vec_Fminmax (sim_cpu *cpu)
NYI_assert (15, 14, 3);
NYI_assert (11, 10, 1);
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
double (* func)(double, double);
if (! full)
HALT_NYI;
- if (uimm (aarch64_get_instr (cpu), 13, 12) == 0)
+ if (INSTR (13, 12) == 0)
func = min ? dminnm : dmaxnm;
- else if (uimm (aarch64_get_instr (cpu), 13, 12) == 3)
+ else if (INSTR (13, 12) == 3)
func = min ? fmin : fmax;
else
HALT_NYI;
@@ -4344,9 +4341,9 @@ do_vec_Fminmax (sim_cpu *cpu)
{
float (* func)(float, float);
- if (uimm (aarch64_get_instr (cpu), 13, 12) == 0)
+ if (INSTR (13, 12) == 0)
func = min ? fminnm : fmaxnm;
- else if (uimm (aarch64_get_instr (cpu), 13, 12) == 3)
+ else if (INSTR (13, 12) == 3)
func = min ? fminf : fmaxf;
else
HALT_NYI;
@@ -4369,10 +4366,10 @@ do_vec_SCVTF (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd. */
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned size = uimm (aarch64_get_instr (cpu), 22, 22);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned size = INSTR (22, 22);
unsigned i;
NYI_assert (29, 23, 0x1C);
@@ -4482,7 +4479,7 @@ do_vec_SCVTF (sim_cpu *cpu)
{ \
if (vm != 0) \
HALT_NYI; \
- if (uimm (aarch64_get_instr (cpu), 22, 22)) \
+ if (INSTR (22, 22)) \
{ \
if (! full) \
HALT_NYI; \
@@ -4505,7 +4502,7 @@ do_vec_SCVTF (sim_cpu *cpu)
#define VEC_FCMP(CMP) \
do \
{ \
- if (uimm (aarch64_get_instr (cpu), 22, 22)) \
+ if (INSTR (22, 22)) \
{ \
if (! full) \
HALT_NYI; \
@@ -4544,31 +4541,31 @@ do_vec_compare (sim_cpu *cpu)
instr[9,5] = Vn
instr[4.0] = Vd. */
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- int size = uimm (aarch64_get_instr (cpu), 23, 22);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ int full = INSTR (30, 30);
+ int size = INSTR (23, 22);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
NYI_assert (28, 24, 0x0E);
NYI_assert (21, 21, 1);
- if ((uimm (aarch64_get_instr (cpu), 11, 11)
- && uimm (aarch64_get_instr (cpu), 14, 14))
- || ((uimm (aarch64_get_instr (cpu), 11, 11) == 0
- && uimm (aarch64_get_instr (cpu), 10, 10) == 0)))
+ if ((INSTR (11, 11)
+ && INSTR (14, 14))
+ || ((INSTR (11, 11) == 0
+ && INSTR (10, 10) == 0)))
{
/* A compare vs 0. */
if (vm != 0)
{
- if (uimm (aarch64_get_instr (cpu), 15, 10) == 0x2A)
+ if (INSTR (15, 10) == 0x2A)
do_vec_maxv (cpu);
- else if (uimm (aarch64_get_instr (cpu), 15, 10) == 0x32
- || uimm (aarch64_get_instr (cpu), 15, 10) == 0x3E)
+ else if (INSTR (15, 10) == 0x32
+ || INSTR (15, 10) == 0x3E)
do_vec_fminmaxV (cpu);
- else if (uimm (aarch64_get_instr (cpu), 29, 23) == 0x1C
- && uimm (aarch64_get_instr (cpu), 21, 10) == 0x876)
+ else if (INSTR (29, 23) == 0x1C
+ && INSTR (21, 10) == 0x876)
do_vec_SCVTF (cpu);
else
HALT_NYI;
@@ -4576,12 +4573,12 @@ do_vec_compare (sim_cpu *cpu)
}
}
- if (uimm (aarch64_get_instr (cpu), 14, 14))
+ if (INSTR (14, 14))
{
/* A floating point compare. */
- unsigned decode = (uimm (aarch64_get_instr (cpu), 29, 29) << 5)
- | (uimm (aarch64_get_instr (cpu), 23, 23) << 4)
- | uimm (aarch64_get_instr (cpu), 13, 10);
+ unsigned decode = (INSTR (29, 29) << 5)
+ | (INSTR (23, 23) << 4)
+ | INSTR (13, 10);
NYI_assert (15, 15, 1);
@@ -4602,8 +4599,8 @@ do_vec_compare (sim_cpu *cpu)
}
else
{
- unsigned decode = (uimm (aarch64_get_instr (cpu), 29, 29) << 6)
- | uimm (aarch64_get_instr (cpu), 15, 10);
+ unsigned decode = (INSTR (29, 29) << 6)
+ | INSTR (15, 10);
switch (decode)
{
@@ -4638,10 +4635,10 @@ do_vec_SSHL (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd. */
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
signed int shift;
@@ -4651,7 +4648,7 @@ do_vec_SSHL (sim_cpu *cpu)
/* FIXME: What is a signed shift left in this context ?. */
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -4722,17 +4719,17 @@ do_vec_USHL (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd */
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
signed int shift;
NYI_assert (29, 24, 0x2E);
NYI_assert (15, 10, 0x11);
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -4803,17 +4800,17 @@ do_vec_FMLA (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (29, 23, 0x1C);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x33);
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
if (! full)
HALT_UNALLOC;
@@ -4847,19 +4844,19 @@ do_vec_max (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (28, 24, 0x0E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x19);
- if (uimm (aarch64_get_instr (cpu), 29, 29))
+ if (INSTR (29, 29))
{
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -4894,7 +4891,7 @@ do_vec_max (sim_cpu *cpu)
}
else
{
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -4943,19 +4940,19 @@ do_vec_min (sim_cpu *cpu)
instr[9,5] = Vm
instr[4.0] = Vd. */
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
+ int full = INSTR (30, 30);
NYI_assert (28, 24, 0x0E);
NYI_assert (21, 21, 1);
NYI_assert (15, 10, 0x1B);
- if (uimm (aarch64_get_instr (cpu), 29, 29))
+ if (INSTR (29, 29))
{
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -4990,7 +4987,7 @@ do_vec_min (sim_cpu *cpu)
}
else
{
- switch (uimm (aarch64_get_instr (cpu), 23, 22))
+ switch (INSTR (23, 22))
{
case 0:
for (i = 0; i < (full ? 16 : 8); i++)
@@ -5039,10 +5036,10 @@ do_vec_sub_long (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = V dest. */
- unsigned size = uimm (aarch64_get_instr (cpu), 23, 22);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned size = INSTR (23, 22);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned bias = 0;
unsigned i;
@@ -5053,7 +5050,7 @@ do_vec_sub_long (sim_cpu *cpu)
if (size == 3)
HALT_UNALLOC;
- switch (uimm (aarch64_get_instr (cpu), 30, 29))
+ switch (INSTR (30, 29))
{
case 2: /* SSUBL2. */
bias = 2;
@@ -5138,11 +5135,11 @@ do_vec_ADDP (sim_cpu *cpu)
FRegister copy_vn;
FRegister copy_vm;
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned size = uimm (aarch64_get_instr (cpu), 23, 22);
- unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned full = INSTR (30, 30);
+ unsigned size = INSTR (23, 22);
+ unsigned vm = INSTR (20, 16);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i, range;
NYI_assert (29, 24, 0x0E);
@@ -5208,38 +5205,38 @@ do_vec_UMOV (sim_cpu *cpu)
instr[9,5] = V source
instr[4,0] = R dest. */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vs = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
unsigned index;
NYI_assert (29, 21, 0x070);
NYI_assert (15, 10, 0x0F);
- if (uimm (aarch64_get_instr (cpu), 16, 16))
+ if (INSTR (16, 16))
{
/* Byte transfer. */
- index = uimm (aarch64_get_instr (cpu), 20, 17);
+ index = INSTR (20, 17);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_vec_u8 (cpu, vs, index));
}
- else if (uimm (aarch64_get_instr (cpu), 17, 17))
+ else if (INSTR (17, 17))
{
- index = uimm (aarch64_get_instr (cpu), 20, 18);
+ index = INSTR (20, 18);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_vec_u16 (cpu, vs, index));
}
- else if (uimm (aarch64_get_instr (cpu), 18, 18))
+ else if (INSTR (18, 18))
{
- index = uimm (aarch64_get_instr (cpu), 20, 19);
+ index = INSTR (20, 19);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_vec_u32 (cpu, vs, index));
}
else
{
- if (uimm (aarch64_get_instr (cpu), 30, 30) != 1)
+ if (INSTR (30, 30) != 1)
HALT_UNALLOC;
- index = uimm (aarch64_get_instr (cpu), 20, 20);
+ index = INSTR (20, 20);
aarch64_set_reg_u64 (cpu, rd, NO_SP,
aarch64_get_vec_u64 (cpu, vs, index));
}
@@ -5257,15 +5254,15 @@ do_vec_FABS (sim_cpu *cpu)
instr[9,5] = Vn
instr[4,0] = Vd. */
- unsigned vn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
+ unsigned vn = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
unsigned i;
NYI_assert (29, 23, 0x1D);
NYI_assert (21, 10, 0x83E);
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
if (! full)
HALT_NYI;
@@ -5293,16 +5290,16 @@ do_vec_FCVTZS (sim_cpu *cpu)
instr[9,5] = Rn
instr[4,0] = Rd. */
- unsigned rn = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned rd = uimm (aarch64_get_instr (cpu), 4, 0);
- unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
+ unsigned rn = INSTR (9, 5);
+ unsigned rd = INSTR (4, 0);
+ unsigned full = INSTR (30, 30);
unsigned i;
NYI_assert (31, 31, 0);
NYI_assert (29, 23, 0x1D);
NYI_assert (21, 10, 0x86E);
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
if (! full)
HALT_UNALLOC;
@@ -5330,16 +5327,16 @@ do_vec_op1 (sim_cpu *cpu)
instr[4,0] = Vd */
NYI_assert (29, 24, 0x0E);
- if (uimm (aarch64_get_instr (cpu), 21, 21) == 0)
+ if (INSTR (21, 21) == 0)
{
- if (uimm (aarch64_get_instr (cpu), 23, 22) == 0)
+ if (INSTR (23, 22) == 0)
{
- if (uimm (aarch64_get_instr (cpu), 30, 30) == 1
- && uimm (aarch64_get_instr (cpu), 17, 14) == 0
- && uimm (aarch64_get_instr (cpu), 12, 10) == 7)
+ if (INSTR (30, 30) == 1
+ && INSTR (17, 14) == 0
+ && INSTR (12, 10) == 7)
return do_vec_ins_2 (cpu);
- switch (uimm (aarch64_get_instr (cpu), 15, 10))
+ switch (INSTR (15, 10))
{
case 0x01: do_vec_DUP_vector_into_vector (cpu); return;
case 0x03: do_vec_DUP_scalar_into_vector (cpu); return;
@@ -5347,7 +5344,7 @@ do_vec_op1 (sim_cpu *cpu)
case 0x0A: do_vec_TRN (cpu); return;
case 0x0F:
- if (uimm (aarch64_get_instr (cpu), 17, 16) == 0)
+ if (INSTR (17, 16) == 0)
{
do_vec_MOV_into_scalar (cpu);
return;
@@ -5373,7 +5370,7 @@ do_vec_op1 (sim_cpu *cpu)
}
}
- switch (uimm (aarch64_get_instr (cpu), 13, 10))
+ switch (INSTR (13, 10))
{
case 0x6: do_vec_UZP (cpu); return;
case 0xE: do_vec_ZIP (cpu); return;
@@ -5383,10 +5380,10 @@ do_vec_op1 (sim_cpu *cpu)
}
}
- switch (uimm (aarch64_get_instr (cpu), 15, 10))
+ switch (INSTR (15, 10))
{
case 0x07:
- switch (uimm (aarch64_get_instr (cpu), 23, 21))
+ switch (INSTR (23, 21))
{
case 1: do_vec_AND (cpu); return;
case 3: do_vec_BIC (cpu); return;
@@ -5409,7 +5406,7 @@ do_vec_op1 (sim_cpu *cpu)
case 0x35: do_vec_fadd (cpu); return;
case 0x2E:
- switch (uimm (aarch64_get_instr (cpu), 20, 16))
+ switch (INSTR (20, 16))
{
case 0x00: do_vec_ABS (cpu); return;
case 0x01: do_vec_FCVTZS (cpu); return;
@@ -5452,29 +5449,29 @@ do_vec_xtl (sim_cpu *cpu)
instr[9,5] = V source
instr[4,0] = V dest. */
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ unsigned vs = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i, shift, bias = 0;
NYI_assert (28, 22, 0x3C);
NYI_assert (15, 10, 0x29);
- switch (uimm (aarch64_get_instr (cpu), 30, 29))
+ switch (INSTR (30, 29))
{
case 2: /* SXTL2, SSHLL2. */
bias = 2;
case 0: /* SXTL, SSHLL. */
- if (uimm (aarch64_get_instr (cpu), 21, 21))
+ if (INSTR (21, 21))
{
- shift = uimm (aarch64_get_instr (cpu), 20, 16);
+ shift = INSTR (20, 16);
aarch64_set_vec_s64
(cpu, vd, 0, aarch64_get_vec_s32 (cpu, vs, bias) << shift);
aarch64_set_vec_s64
(cpu, vd, 1, aarch64_get_vec_s32 (cpu, vs, bias + 1) << shift);
}
- else if (uimm (aarch64_get_instr (cpu), 20, 20))
+ else if (INSTR (20, 20))
{
- shift = uimm (aarch64_get_instr (cpu), 19, 16);
+ shift = INSTR (19, 16);
bias *= 2;
for (i = 0; i < 4; i++)
aarch64_set_vec_s32
@@ -5484,7 +5481,7 @@ do_vec_xtl (sim_cpu *cpu)
{
NYI_assert (19, 19, 1);
- shift = uimm (aarch64_get_instr (cpu), 18, 16);
+ shift = INSTR (18, 16);
bias *= 3;
for (i = 0; i < 8; i++)
aarch64_set_vec_s16
@@ -5495,17 +5492,17 @@ do_vec_xtl (sim_cpu *cpu)
case 3: /* UXTL2, USHLL2. */
bias = 2;
case 1: /* UXTL, USHLL. */
- if (uimm (aarch64_get_instr (cpu), 21, 21))
+ if (INSTR (21, 21))
{
- shift = uimm (aarch64_get_instr (cpu), 20, 16);
+ shift = INSTR (20, 16);
aarch64_set_vec_u64
(cpu, vd, 0, aarch64_get_vec_u32 (cpu, vs, bias) << shift);
aarch64_set_vec_u64
(cpu, vd, 1, aarch64_get_vec_u32 (cpu, vs, bias + 1) << shift);
}
- else if (uimm (aarch64_get_instr (cpu), 20, 20))
+ else if (INSTR (20, 20))
{
- shift = uimm (aarch64_get_instr (cpu), 19, 16);
+ shift = INSTR (19, 16);
bias *= 2;
for (i = 0; i < 4; i++)
aarch64_set_vec_u32
@@ -5515,7 +5512,7 @@ do_vec_xtl (sim_cpu *cpu)
{
NYI_assert (19, 19, 1);
- shift = uimm (aarch64_get_instr (cpu), 18, 16);
+ shift = INSTR (18, 16);
bias *= 3;
for (i = 0; i < 8; i++)
aarch64_set_vec_u16
@@ -5537,17 +5534,17 @@ do_vec_SHL (sim_cpu *cpu)
instr [4, 0] = Vd. */
int shift;
- int full = uimm (aarch64_get_instr (cpu), 30, 30);
- unsigned vs = uimm (aarch64_get_instr (cpu), 9, 5);
- unsigned vd = uimm (aarch64_get_instr (cpu), 4, 0);
+ int full = INSTR (30, 30);
+ unsigned vs = INSTR (9, 5);
+ unsigned vd = INSTR (4, 0);
unsigned i;
NYI_assert (29, 23, 0x1E);
NYI_assert (15, 10, 0x15);
- if (uimm (aarch64_get_instr (cpu), 22, 22))
+ if (INSTR (22, 22))
{
- shift = uimm (aarch64_get_instr (cpu), 21, 16);
+ shift = INSTR (21, 16);
if (full == 0)
HALT_UNALLOC;
@@ -5561,9 +5558,9 @@ do_vec_SHL (sim_cpu *cpu)
return;
}
- if (uimm (aarch64_get_instr (cpu), 21, 21))
+ if (INSTR (21, 21))
{
- shift = uimm (aarch64_get_instr (cpu), 20, 16);
+ shift = INSTR (20, 16);
for (i = 0; i < (full ? 4 : 2); i++)
{
@@ -5574,9 +5571,9 @@ do_vec_SHL (sim_cpu *cpu)
return;
}
- if (uimm (aarch64_get_instr (cpu), 20, 20[...]
[diff truncated at 100000 bytes]