src/sim arm/ChangeLog arm/wrapper.c avr/interp ...

[vapier at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	vapier@sourceware.org	2010-04-14 07:38:06

Modified files:
	sim/arm        : ChangeLog wrapper.c 
	sim/avr        : interp.c 
	sim/cr16       : ChangeLog interp.c 
	sim/d10v       : ChangeLog interp.c 
	sim/erc32      : ChangeLog interf.c 
	sim/h8300      : ChangeLog compile.c 
	sim/m32c       : ChangeLog gdb-if.c mem.c mem.h 
	sim/mcore      : ChangeLog interp.c 
	sim/microblaze : interp.c 
	sim/mips       : ChangeLog interp.c 
	sim/moxie      : ChangeLog interp.c 
	sim/ppc        : ChangeLog sim_calls.c 
	sim/rx         : ChangeLog gdb-if.c 
	sim/sh         : ChangeLog interp.c 
Added files:
	sim/avr        : ChangeLog 
	sim/microblaze : ChangeLog 

Log message:
	sim: constify sim_write source buffer (part 2)
	
	As pointed out by Sandra Loosemore, a bunch of targets define sim_write
	themselves instead of using the common/ code.  So constify them too.
	
	Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/arm/ChangeLog.diff?cvsroot=src&r1=1.105&r2=1.106
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/arm/wrapper.c.diff?cvsroot=src&r1=1.38&r2=1.39
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/avr/ChangeLog.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/avr/interp.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cr16/ChangeLog.diff?cvsroot=src&r1=1.8&r2=1.9
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cr16/interp.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/d10v/ChangeLog.diff?cvsroot=src&r1=1.41&r2=1.42
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/d10v/interp.c.diff?cvsroot=src&r1=1.18&r2=1.19
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/ChangeLog.diff?cvsroot=src&r1=1.30&r2=1.31
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/interf.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/h8300/ChangeLog.diff?cvsroot=src&r1=1.65&r2=1.66
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/h8300/compile.c.diff?cvsroot=src&r1=1.46&r2=1.47
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/ChangeLog.diff?cvsroot=src&r1=1.18&r2=1.19
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/gdb-if.c.diff?cvsroot=src&r1=1.9&r2=1.10
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/mem.c.diff?cvsroot=src&r1=1.11&r2=1.12
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/mem.h.diff?cvsroot=src&r1=1.8&r2=1.9
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mcore/ChangeLog.diff?cvsroot=src&r1=1.23&r2=1.24
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mcore/interp.c.diff?cvsroot=src&r1=1.12&r2=1.13
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/microblaze/ChangeLog.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/microblaze/interp.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/ChangeLog.diff?cvsroot=src&r1=1.156&r2=1.157
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/interp.c.diff?cvsroot=src&r1=1.25&r2=1.26
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/moxie/ChangeLog.diff?cvsroot=src&r1=1.12&r2=1.13
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/moxie/interp.c.diff?cvsroot=src&r1=1.10&r2=1.11
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/ppc/ChangeLog.diff?cvsroot=src&r1=1.99&r2=1.100
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/ppc/sim_calls.c.diff?cvsroot=src&r1=1.12&r2=1.13
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/ChangeLog.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/gdb-if.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/sh/ChangeLog.diff?cvsroot=src&r1=1.62&r2=1.63
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/sh/interp.c.diff?cvsroot=src&r1=1.21&r2=1.22