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src/sim/sh ChangeLog gencode.c


CVSROOT:	/cvs/src
Module name:	src
Changes by:	msnyder@sourceware.org	2003-07-23 21:25:41

Modified files:
	sim/sh         : ChangeLog gencode.c 

Log message:
	2003-06-27  Michael Snyder  <msnyder@redhat.com>
	
	* gencode.c (op tab): Some fix-ups of refs and defs.
	(ocbi, ocbp): Cache not simulated, but may cause memory fault.
	(gensym_caselist): Add default case to switch statement.
	(expand_ppi_code): Add default case to switch statement.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/ChangeLog.diff?cvsroot=src&r1=1.18&r2=1.19
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/gencode.c.diff?cvsroot=src&r1=1.11&r2=1.12


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