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>
> gas out of binutils-2.9.1.0.23 (and older versions) has a severe bug
> for the SPARC platform (sparc-sun-solaris2.6), i.e. it generates
> wrong code for
>
> sethi 0x4000,%i0
>
> (and probably in all other cases where sethi is used without the
> %hi(...)-construct).
>
> The sethi instruction has following suggested assembly syntax
> (see SPARC Architecture Manual):
>
> sethi const22,reg
>
> const22 is a 22-bit constant that is placed by sethi in the most
> significant 22 bits of reg (while it zeroes the 10 least significant
> bits of reg). Therefore we would expect the value 0x100000 in %i0
> after the execution of ``sethi 16384''. Instead of this, gas
> modifies the given constant such that 0x4000 will be found in %i0
> afterwards. This would have been equivalent to
>
> sethi %hi(0x4000),%i0
>
Hi,
Here is a new patch. Please discard my last patch to tc-sparc.c.
Let me know what you get.
Thanks.
H.J.
---
Fri Apr 2 16:05:25 1999 H.J. Lu (hjl@gnu.org)
* sparc-opc.c: Change "sethi" from "h,d" to "n,d".
Index: ChangeLog.linux
===================================================================
RCS file: /local/work/cvs/gnu/binutils/opcodes/ChangeLog.linux,v
retrieving revision 1.40
diff -u -p -r1.40 ChangeLog.linux
--- ChangeLog.linux 1999/03/31 17:24:49 1.40
+++ ChangeLog.linux 1999/04/03 00:05:33
@@ -1,3 +1,5 @@
+Fri Apr 2 16:05:25 1999 H.J. Lu (hjl@gnu.org)
+
Sun Mar 28 11:48:17 1999 H.J. Lu (hjl@gnu.org)
* i386-dis.c (INSN_FWAIT): New, defined.
Index: sparc-opc.c
===================================================================
RCS file: /local/work/cvs/gnu/binutils/opcodes/sparc-opc.c,v
retrieving revision 1.7
diff -u -p -r1.7 sparc-opc.c
--- sparc-opc.c 1998/12/05 03:38:56 1.7
+++ sparc-opc.c 1999/04/03 00:00:22
@@ -1379,7 +1379,7 @@ CONDFC ("fbule", "cb013", 0xe, 0),
{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 },
{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
-{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
+{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "n,d", 0, v6 },
{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 },