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Maximum Alignment Restrictions

What is the rationale for the maximum alignment supported on a particular 
CPU family?  

My current problem is that the SPARC trap table must be on a 4K boundary
but that appears to be too large. 

My thinking is that there is no particular reason (except object format 
limitations) to place a CPU dependent limit on maximum alignment boundary.

Just curious.

| Joel Sherrill                          | Sr. Computer Scientist         |
|      | On-Line Applications Research  |
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|   multiprocessor executive!            | (205) 883-0131                 |