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[Bug 1001117] Cortex-M architecture fixes.


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--- Comment #2 from Ilija Kocho <ilijak@siva.com.mk> 2011-01-16 14:06:08 GMT ---
Hi Christophe

You seem to be right on both points. #1 should not be here and #2 is simply
swapped sources, shame on me :( .

Since you already have the Bug 1001090 let's continue discussion on SysTick
there. Also, considering that you are working on a yet another platform,
Stellaris,we could share some info on eventual similar Cortex-M architecture
issues and try to synchronize action.

Regarding this bug, I am going to put a patch that covers VTOR only.

Ilija

(In reply to comment #1)
> Hi Ilija,
> 
> I made a patch for the system tick clock source some time ago: Bug 1001090 .
> 
> Your patch seems to change the default behavior of the cortex M HAL:
> 
> #1 CSR is initialised with CYGARC_REG_SYSTICK_CSR_TICKINT so you are enabling
> the interrupt.
> 
> #2 Definition of CYGARC_REG_SYSTICK_CSR_CLK_EXT and
> CYGARC_REG_SYSTICK_CSR_CLK_INT was originally correct, your new definition is
> more difficult to understand. When CYGARC_REG_SYSTICK_CSR_CLK_SRC is not
> defined in CDLs, the clock source equal CYGARC_REG_SYSTICK_CSR_CLK_INT which
> actually makes the processor use external clock while by reading the code one
> might think that the processor should use internal clock.
> 
> +#if !defined CYGARC_REG_SYSTICK_CSR_CLK_SRC
> +#define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_INT
> +#endif
> 
> Christophe

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