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MPC8xx SMC serial fix


Attached patch fixes errors with SMC config on an 866. If you tried to use the SMC in any setting other than 8, none, 1 the CLEN field in SMCMR was set incorrectly.

Also added the beginnings of some basic error detection when the SMC reports a frame or parity error.

Tested on MPC866P hardware, all serial combinations with even/odd parity, 1 or 2 stop bits, 7 or 8 data bits (had no hardware to test 5 & 6).

--
------------------------------------------------------------------------
Will Wagner                                     will_wagner@carallon.com
Senior Project Engineer                        Office Tel: 0207 371 2032
Carallon Ltd, Studio G20, Shepherds Building, Rockley Rd, London W14 0DA
------------------------------------------------------------------------
Index: devs/serial/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.23
diff -u -w -b -r1.23 ChangeLog
--- devs/serial/powerpc/quicc/current/ChangeLog	17 May 2004 09:35:37 -0000	1.23
+++ devs/serial/powerpc/quicc/current/ChangeLog	27 Jan 2006 17:11:33 -0000
@@ -1,3 +1,9 @@
+2006-01-27 Will Wagner <willw@carallon.com>
+
+        * src/quicc_smc_serial.h: Removed unused structure
+        * src/quicc_smc_serial.c(quicc_smc_serial_config_port): Corrected CLEN in SMCMR
+        * src/quicc_smc_serial.c(quicc_smc_serial_DSR & quicc_scc_serial_DSR): Better handling of frame and parity errors
+
 2004-05-10  Robert Chenault <robertchenault@yahoo.com>
 
 	* src/quicc_smc_serial.h: Added two casts of (int) on
Index: hal/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.36
diff -u -w -b -r1.36 ChangeLog
--- hal/powerpc/quicc/current/ChangeLog	5 Apr 2004 16:02:11 -0000	1.36
+++ hal/powerpc/quicc/current/ChangeLog	27 Jan 2006 17:13:33 -0000
@@ -1,3 +1,8 @@
+2006-01-27 Will Wagner <willw@carallon.com>
+
+        * include/ppc8xx.h: Add definition for frame and parity errors in BD ctrl.
+        Changed macro calculating SMCMR CLEN.
+        
 2004-04-01  Robert Chenault  <robertchenault@yahoo.com>
 
 	* include/ppc8xx.h: Add definition for 8 bytes to spi_pram structure
Index: hal/powerpc/quicc/current/include/ppc8xx.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/powerpc/quicc/current/include/ppc8xx.h,v
retrieving revision 1.15
diff -u -w -b -r1.15 ppc8xx.h
--- hal/powerpc/quicc/current/include/ppc8xx.h	5 Apr 2004 16:02:13 -0000	1.15
+++ hal/powerpc/quicc/current/include/ppc8xx.h	27 Jan 2006 16:41:40 -0000
@@ -968,6 +968,8 @@
 #define QUICC_BD_CTL_Wrap           0x2000  // Last buffer in list
 #define QUICC_BD_CTL_Int            0x1000  // Generate interrupt when empty (tx) or full (rx)
 #define QUICC_BD_CTL_Last           0x0800  // Last buffer in a sequence
+#define QUICC_BD_CTL_Frame          0x0010  // Framing Error
+#define QUICC_BD_CTL_Parity         0x0008  // Parity Error
 #define QUICC_BD_CTL_MASK           0xB000  // User settable bits
 
 // Command register
@@ -996,7 +998,7 @@
 #define QUICC_SMCE_RX               0x01  // Rx interrupt
 
 // SMC Mode Register
-#define QUICC_SMCMR_CLEN(n)   ((n+1)<<11)   // Character length
+#define QUICC_SMCMR_CLEN(n)   (n<<11)       // Character length + parity + stop bits
 #define QUICC_SMCMR_SB(n)     ((n-1)<<10)   // Stop bits (1 or 2)
 #define QUICC_SMCMR_PE(n)     (n<<9)        // Parity enable (0=disable, 1=enable)
 #define QUICC_SMCMR_PM(n)     (n<<8)        // Parity mode (0=odd, 1=even)
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.18
diff -u -w -b -r1.18 quicc_smc_serial.c
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	9 Feb 2004 16:33:43 -0000	1.18
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	27 Jan 2006 16:39:31 -0000
@@ -345,7 +345,7 @@
     ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
     HAL_IO_BARRIER();  // Inforce I/O ordering
     // Disable port interrupts while changing hardware
-    _lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | 
+    _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
         smc_select_stop_bits[new_config->stop] |
         smc_select_parity[new_config->parity];
     // Stop transmitter while changing baud rate
@@ -974,9 +974,17 @@
             (char *)eppc_base() + pram->rbptr );
         while (rxbd != rxlast) {
             if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) {
+                if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) {
                 for (i = 0;  i < rxbd->length;  i++) {
                     (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
                 }
+                }
+                else
+                {
+                    // is this necessary?
+                    rxbd->ctrl &= QUICC_BD_CTL_MASK;
+                    // should we report the error?
+                }
                 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
                 HAL_DCACHE_IS_ENABLED(cache_state);
                 if (cache_state) {
@@ -1035,9 +1043,17 @@
         rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr);
         while (rxbd != rxlast) {
             if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) {
+                if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) {
                 for (i = 0;  i < rxbd->length;  i++) {
                     (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
                 }
+                }
+                else
+                {
+                    // is this necessary?
+                    rxbd->ctrl &= QUICC_BD_CTL_MASK;
+                    // should we report the error?
+                }
                 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
                 HAL_DCACHE_IS_ENABLED(cache_state);
                 if (cache_state) {
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h,v
retrieving revision 1.7
diff -u -w -b -r1.7 quicc_smc_serial.h
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h	17 May 2004 09:35:38 -0000	1.7
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h	27 Jan 2006 16:41:16 -0000
@@ -58,13 +58,6 @@
 
 #include <cyg/hal/quicc/ppc8xx.h>                  // QUICC structure definitions
 
-static unsigned int smc_select_word_length[] = {
-    QUICC_SMCMR_CLEN(5),  // 5 bits / word (char)
-    QUICC_SMCMR_CLEN(6),
-    QUICC_SMCMR_CLEN(7),
-    QUICC_SMCMR_CLEN(8)
-};
-
 static unsigned int smc_select_stop_bits[] = {
     0, 
     QUICC_SMCMR_SB(1),   // 1 stop bit

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