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RE: [ECOS] Re: ISR not causing an DSR in some rare conditions
- From: Jay Foster <jay at systech dot com>
- To: Jay Foster <jay at systech dot com>, 'Sergei O rganov' <osv at javad dot com>, Gary Thomas <gary at mlbassoc dot com>
- Cc: 'ecos-patches at ecos dot sourceware dot org' <ecos-patches at ecos dot sourceware dot org>
- Date: Fri, 20 Jan 2006 09:51:12 -0800
- Subject: RE: [ECOS] Re: ISR not causing an DSR in some rare conditions
I've re-examined this patch, and have noticed that it does not 'exactly'
result in the same operation as the original code.
The original code:
sub ip,sp,#20
stmfd ip!,{sp,lr}
mov sp,ip
stmfd sp!,{r0-r10,fp,ip}
The proposed code:
mov ip,sp
sub sp,sp,#(ARMREG_SIZE - armreg_pc) // skip svc_sp, svc_lr,
vector, cpsr, and pc
stmfd sp!,{ip,lr}
stmfd sp!,{r0-r10,fp,ip}
Note that the value of 'ip' saved on the stack by the 4th instruction
(stmfd) is different for these two cases. In the original code, 'ip' was
the same as the sp just prior to the stmfd instruction. In the proposed
code, 'ip' is the same as the sp upon entry to the function.
By adding an extra instruction, this can be corrected to be the same:
mov ip,sp
sub sp,sp,#(ARMREG_SIZE - armreg_pc) // skip svc_sp, svc_lr,
vector, cpsr, and pc
stmfd sp!,{ip,lr}
mov ip,sp
stmfd sp!,{r0-r10,fp,ip}
It doesn't appear to make any difference. Is this because it doesn't
matter? If it doesn't matter, then there is no reason to add the extra mov
instruction. Are interrupts even enabled on entry to this function? If
not, then none of this matters.
Jay
-----Original Message-----
From: Jay Foster [mailto:jay@systech.com]
Sent: Wednesday, January 18, 2006 3:16 PM
To: 'Sergei Organov'; Gary Thomas
Cc: 'ecos-patches@ecos.sourceware.org'
Subject: RE: [ECOS] Re: ISR not causing an DSR in some rare conditions
Attached is a patch for the first problem described below. This is
essentially Sergei Organov's suggested change put into patch form.
Jay
-----Original Message-----
From: Sergei Organov [mailto:osv@javad.com]
Sent: Thursday, January 12, 2006 10:24 AM
To: Gary Thomas
Cc: ecos-discuss@ecos.sourceware.org
Subject: Re: [ECOS] Re: ISR not causing an DSR in some rare conditions
Gary Thomas <gary@mlbassoc.com> writes:
> On Thu, 2006-01-12 at 19:11 +0300, Sergei Organov wrote:
> <...snip>
>>
>> BTW, if it runs on ARM, do you use FIQ? I think I know at least 2 bugs
>> in the ARM HAL, one of which is with FIQ handling (and another one being
>> in the context switch), but chances are very low they show themselves
>> the way you see.
>
> What bugs are you speaking of?
> Do you have patches that fix them?
Well, one of them is the first item here:
<http://article.gmane.org/gmane.os.ecos.general/16715/match=arm+hal+issues>
Another one, that is FIQ related, hasn't yet been reported, but I
can prepare a problem description and a patch to fix it, though I'd
appreciate some response to my 2 month old message mentioned above
first.
-- Sergei.
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