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PowerPC - improve MPC8xx & QUICC
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 23 Mar 2003 09:23:21 -0700
- Subject: PowerPC - improve MPC8xx & QUICC
Note: still need to improve how the serial ports are "configured"
(pin layouts, etc).
Index: devs/serial/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.15
diff -u -5 -p -r1.15 ChangeLog
--- devs/serial/powerpc/quicc/current/ChangeLog 17 Mar 2003 22:17:35 -0000 1.15
+++ devs/serial/powerpc/quicc/current/ChangeLog 23 Mar 2003 16:06:54 -0000
@@ -1,5 +1,14 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/quicc_smc_serial.h: Move common definitions to common
+ include file (in HAL).
+
+ * src/quicc_smc_serial.c:
+ * cdl/ser_quicc_smc.cdl: Remove options for baud rate generator
+ assignment - use more generic [automatic] support.
+
2003-03-17 Gary Thomas <gary at mlbassoc dot com>
* src/quicc_smc_serial.h:
* src/quicc_smc_serial.c:
* cdl/ser_quicc_smc.cdl: Add support for SCC1/SCC2/SCC3. Inspired
Index: devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl,v
retrieving revision 1.8
diff -u -5 -p -r1.8 ser_quicc_smc.cdl
--- devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl 17 Mar 2003 22:17:35 -0000 1.8
+++ devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl 23 Mar 2003 12:09:16 -0000
@@ -111,20 +111,10 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
description "
This option specifies the size of the internal buffers used
for the PowerPC QUICC/SMC port 1."
}
- cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG {
- display "Which baud rate generator to use for the PowerPC QUICC/SMC serial port 1"
- flavor data
- legal_values 1 to 4
- default_value 1
- description "
- This option specifies which of the four baud rate generators
- to use for the PowerPC QUICC/SMC port 1."
- }
-
cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE {
display "Output buffer size for the PowerPC QUICC/SMC serial port 1"
flavor data
legal_values 16 to 128
default_value 16
@@ -202,20 +192,10 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
description "
This option specifies the size of the internal buffers used
for the PowerPC QUICC/SMC port 2."
}
- cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG {
- display "Which baud rate generator to use for the PowerPC QUICC/SMC serial port 2"
- flavor data
- legal_values 1 to 4
- default_value 2
- description "
- This option specifies which of the four baud rate generators
- to use for the PowerPC QUICC/SMC port 2."
- }
-
cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE {
display "Output buffer size for the PowerPC QUICC/SMC serial port 2"
flavor data
legal_values 16 to 128
default_value 16
@@ -326,20 +306,10 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
description "
This option specifies the size of the internal buffers used
for the PowerPC QUICC/SCC port 1."
}
- cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BRG {
- display "Which baud rate generator to use for the PowerPC QUICC/SCC serial port 1"
- flavor data
- legal_values 1 to 4
- default_value 2
- description "
- This option specifies which of the four baud rate generators
- to use for the PowerPC QUICC/SCC port 1."
- }
-
cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE {
display "Output buffer size for the PowerPC QUICC/SCC serial port 1"
flavor data
legal_values 16 to 128
default_value 16
@@ -417,20 +387,10 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
description "
This option specifies the size of the internal buffers used
for the PowerPC QUICC/SCC port 2."
}
- cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BRG {
- display "Which baud rate generator to use for the PowerPC QUICC/SCC serial port 2"
- flavor data
- legal_values 1 to 4
- default_value 3
- description "
- This option specifies which of the four baud rate generators
- to use for the PowerPC QUICC/SCC port 2."
- }
-
cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE {
display "Output buffer size for the PowerPC QUICC/SCC serial port 2"
flavor data
legal_values 16 to 128
default_value 16
@@ -506,20 +466,10 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
legal_values 0 to 8192
default_value 256
description "
This option specifies the size of the internal buffers used
for the PowerPC QUICC/SCC port 3."
- }
-
- cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BRG {
- display "Which baud rate generator to use for the PowerPC QUICC/SCC serial port 3"
- flavor data
- legal_values 1 to 4
- default_value 4
- description "
- This option specifies which of the four baud rate generators
- to use for the PowerPC QUICC/SCC port 3."
}
cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE {
display "Output buffer size for the PowerPC QUICC/SCC serial port 3"
flavor data
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.11
diff -u -5 -p -r1.11 quicc_smc_serial.c
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 17 Mar 2003 22:17:35 -0000 1.11
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 23 Mar 2003 15:52:11 -0000
@@ -72,11 +72,11 @@
typedef struct quicc_sxx_serial_info {
CYG_ADDRWORD channel; // Which channel SMCx/SCCx
short int_num; // Interrupt number
short type; // Channel type - SCC or SMC
- cyg_uint32 *brg; // Which baud rate generator
+ unsigned long *brg; // Which baud rate generator
void *pram; // Parameter RAM pointer
void *ctl; // SMC/SCC control registers
volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use
struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor
int txsize, rxsize; // Length of individual buffers
@@ -372,46 +372,24 @@ quicc_smc_serial_init_info(quicc_sxx_ser
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF,
int portBmask,
- int BRG, int SIpos)
+ int port)
{
EPPC *eppc = eppc_base();
struct cp_bufdesc *txbd, *rxbd;
- cyg_uint32 simode = 0;
int i;
// Disable channel during setup
ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
smc_chan->pram = (void *)uart_pram;
smc_chan->ctl = (void *)ctl;
- /*
- * SDMA & LCD bus request level 5
- * (Section 16.10.2.1)
- */
- eppc->dma_sdcr = 1;
- switch (BRG) {
- case 1:
- smc_chan->brg = (cyg_uint32 *)&eppc->brgc1;
- simode = 0;
- break;
- case 2:
- smc_chan->brg = (cyg_uint32 *)&eppc->brgc2;
- simode = 1;
- break;
- case 3:
- smc_chan->brg = (cyg_uint32 *)&eppc->brgc3;
- simode = 2;
- break;
- case 4:
- smc_chan->brg = (cyg_uint32 *)&eppc->brgc4;
- simode = 3;
- break;
- }
- // NMSI mode, BRGn to SMCm (Section 16.12.5.2)
- eppc->si_simode = (eppc->si_simode & ~(0xF<<SIpos)) | (simode<<SIpos);
+
+ // Set up baud rate generator
+ smc_chan->brg = _mpc8xx_allocate_brg(port);
+
/*
* Set up the PortB pins for UART operation.
* Set PAR and DIR to allow SMCTXDx and SMRXDx
* (Table 16-39)
*/
@@ -526,46 +504,24 @@ quicc_scc_serial_init_info(quicc_sxx_ser
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF,
int portAmask, int portBmask, int portCmask,
- int BRG, int SIpos)
+ int port)
{
EPPC *eppc = eppc_base();
struct cp_bufdesc *txbd, *rxbd;
- cyg_uint32 simode = 0;
int i;
// Disable channel during setup
ctl->scc_gsmr_l = 0;
scc_chan->pram = (void *)uart_pram;
scc_chan->ctl = (void *)ctl;
- /*
- * SDMA & LCD bus request level 5
- * (Section 16.10.2.1)
- */
- eppc->dma_sdcr = 1;
- switch (BRG) {
- case 1:
- scc_chan->brg = (cyg_uint32 *)&eppc->brgc1;
- simode = 0;
- break;
- case 2:
- scc_chan->brg = (cyg_uint32 *)&eppc->brgc2;
- simode = 1;
- break;
- case 3:
- scc_chan->brg = (cyg_uint32 *)&eppc->brgc3;
- simode = 2;
- break;
- case 4:
- scc_chan->brg = (cyg_uint32 *)&eppc->brgc4;
- simode = 3;
- break;
- }
- // Route baud rate generators
- eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<SIpos)) | (((simode<<3)|(simode<<0))<<SIpos);
+
+ // Set up baud rate generator
+ scc_chan->brg = _mpc8xx_allocate_brg(port);
+
/*
* Set up the PortA/B/C pins for UART operation.
*/
eppc->pio_papar |= portAmask;
eppc->pio_padir &= ~portAmask;
@@ -680,12 +636,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0]),
0xC0, // PortB mask
- CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
- 12 // SI mask position
+ QUICC_CPM_SMC1
);
}
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
if (chan == &quicc_sxx_serial_channel_smc2) {
@@ -701,12 +656,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0][0]),
0xC00, // PortB mask
- CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG,
- 28 // SI mask position
+ QUICC_CPM_SMC2
);
}
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1
if (chan == &quicc_sxx_serial_channel_scc1) {
@@ -724,12 +678,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE,
ALIGN_TO_CACHELINES(&quicc_scc1_rxbuf[0][0]),
0x0003, // PortA mask
0x1000, // PortB mask
0x0800, // PortC mask
- CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BRG,
- 0 // SI mask position
+ QUICC_CPM_SCC1
);
}
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC2
if (chan == &quicc_sxx_serial_channel_scc2) {
@@ -747,12 +700,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE,
ALIGN_TO_CACHELINES(&quicc_scc2_rxbuf[0][0]),
0x000C, // PortA mask
0x2000, // PortB mask
0x0C00, // PortC mask
- CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BRG,
- 8 // SI mask position
+ QUICC_CPM_SCC2
);
}
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC3
if (chan == &quicc_sxx_serial_channel_scc3) {
@@ -770,12 +722,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE,
ALIGN_TO_CACHELINES(&quicc_scc3_rxbuf[0][0]),
0x0000, // PortA mask
0x00C0, // PortB mask
0x0000, // PortC mask
- CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BRG,
- 16 // SI mask position
+ QUICC_CPM_SCC3
);
}
#endif
(chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
if (chan->out_cbuf.len != 0) {
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h,v
retrieving revision 1.4
diff -u -5 -p -r1.4 quicc_smc_serial.h
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h 17 Mar 2003 22:17:35 -0000 1.4
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h 22 Mar 2003 13:23:29 -0000
@@ -56,35 +56,10 @@
// Description of serial ports using QUICC/SMC
#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
-// SMC Mode Register
-#define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length
-#define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
-#define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
-#define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
-#define QUICC_SMCMR_UART (2<<4) // UART mode
-#define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
-#define QUICC_SMCMR_REN (1<<0) // Enable receiver
-
-// SMC Events (interrupts)
-#define QUICC_SMCE_BRK 0x10 // Break received
-#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
-#define QUICC_SMCE_TX 0x02 // Tx interrupt
-#define QUICC_SMCE_RX 0x01 // Rx interrupt
-
-// SMC Commands
-#define QUICC_SMC_CMD_InitTxRx (0<<8)
-#define QUICC_SMC_CMD_InitTx (1<<8)
-#define QUICC_SMC_CMD_InitRx (2<<8)
-#define QUICC_SMC_CMD_StopTx (4<<8)
-#define QUICC_SMC_CMD_RestartTx (6<<8)
-#define QUICC_SMC_CMD_Reset 0x8000
-#define QUICC_SMC_CMD_Go 0x0001
-
-
static unsigned int smc_select_word_length[] = {
QUICC_SMCMR_CLEN(5), // 5 bits / word (char)
QUICC_SMCMR_CLEN(6),
QUICC_SMCMR_CLEN(7),
QUICC_SMCMR_CLEN(8)
@@ -102,34 +77,10 @@ static unsigned int smc_select_parity[]
QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(1), // Even parity
QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(0), // Odd parity
0, // Mark parity
0, // Space parity
};
-
-// SCC PSMR masks ....
-#define QUICC_SCC_PSMR_ASYNC 0x8000
-#define QUICC_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb)
-#define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8)
-#define QUICC_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled)
-#define QUICC_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high)
-#define QUICC_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high)
-
-// SCC DSR masks
-#define QUICC_SCC_DSR_FULL 0x7e7e
-#define QUICC_SCC_DSR_HALF 0x467e
-
-// SCC GSMR masks ...
-#define QUICC_SCC_GSMR_H_INIT 0x00000060
-#define QUICC_SCC_GSMR_L_INIT 0x00028004
-#define QUICC_SCC_GSMR_L_Tx 0x00000010
-#define QUICC_SCC_GSMR_L_Rx 0x00000020
-
-// SCC Events (interrupts)
-#define QUICC_SCCE_BRK 0x0040
-#define QUICC_SCCE_BSY 0x0004
-#define QUICC_SCCE_TX 0x0002
-#define QUICC_SCCE_RX 0x0001
static unsigned int scc_select_word_length[] = {
QUICC_SCC_PSMR_CLEN(5), // 5 bits / word (char)
QUICC_SCC_PSMR_CLEN(6),
QUICC_SCC_PSMR_CLEN(7),
Index: hal/powerpc/adder/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/ChangeLog,v
retrieving revision 1.6
diff -u -5 -p -r1.6 ChangeLog
--- hal/powerpc/adder/current/ChangeLog 23 Mar 2003 01:56:19 -0000 1.6
+++ hal/powerpc/adder/current/ChangeLog 23 Mar 2003 16:08:14 -0000
@@ -1,5 +1,9 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * cdl/hal_powerpc_adder.cdl: New option for setting processor type.
+
2003-03-20 Gary Thomas <gary at mlbassoc dot com>
* src/hal_aux.c (hal_platform_init): Fix SCC2/SCC3 routing.
2003-03-11 Mark Salter <msalter at redhat dot com>
Index: hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl,v
retrieving revision 1.3
diff -u -5 -p -r1.3 hal_powerpc_adder.cdl
--- hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 31 Jan 2003 15:14:50 -0000 1.3
+++ hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 23 Mar 2003 13:26:47 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -65,10 +65,12 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER {
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGNUM_HAL_QUICC_SMC2
implements CYGNUM_HAL_QUICC_SCC3
+
+ requires { CYGHWR_HAL_POWERPC_MPC8XX == "850" }
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_adder.h>"
Index: hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm,v
retrieving revision 1.2
diff -u -5 -p -r1.2 redboot_ROMRAM.ecm
--- hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm 26 Nov 2002 13:48:18 -0000 1.2
+++ hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm 23 Mar 2003 16:17:07 -0000
@@ -17,10 +17,11 @@ cdl_configuration eCos {
package -hardware CYGPKG_HAL_QUICC current ;
package -hardware CYGPKG_DEVS_FLASH_POWERPC_ADDER current ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_QUICC current ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_ADDER current ;
+ package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_ISOINFRA current ;
package -template CYGPKG_LIBC_STRING current ;
@@ -50,10 +51,14 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_
inferred_value 1
};
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
+};
+
+cdl_component CYGHWR_HAL_POWERPC_MPC8XX {
+ inferred_value 850
};
cdl_component CYG_HAL_STARTUP {
user_value ROMRAM
};
Index: hal/powerpc/cogent/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/cogent/current/ChangeLog,v
retrieving revision 1.25
diff -u -5 -p -r1.25 ChangeLog
--- hal/powerpc/cogent/current/ChangeLog 7 Mar 2003 14:47:30 -0000 1.25
+++ hal/powerpc/cogent/current/ChangeLog 23 Mar 2003 16:07:40 -0000
@@ -1,5 +1,9 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * cdl/hal_powerpc_cogent.cdl: New options for setting processor type.
+
2003-03-07 Gary Thomas <gary at mlbassoc dot com>
* include/plf_stub.h: Remove [confusing] platform specific include.
2002-08-06 Gary Thomas <gary at chez-thomas dot org>
Index: hal/powerpc/cogent/current/cdl/hal_powerpc_cogent.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/cogent/current/cdl/hal_powerpc_cogent.cdl,v
retrieving revision 1.6
diff -u -5 -p -r1.6 hal_powerpc_cogent.cdl
--- hal/powerpc/cogent/current/cdl/hal_powerpc_cogent.cdl 23 May 2002 23:04:17 -0000 1.6
+++ hal/powerpc/cogent/current/cdl/hal_powerpc_cogent.cdl 23 Mar 2003 16:07:47 -0000
@@ -7,10 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -62,10 +63,12 @@ cdl_package CYGPKG_HAL_POWERPC_COGENT {
compile hal_diag.c plf_misc.c cogent.S plf_stub.c
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ requires { CYGHWR_HAL_POWERPC_MPC8XX == "823" }
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_cogent.h>"
}
Index: hal/powerpc/mbx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mbx/current/ChangeLog,v
retrieving revision 1.34
diff -u -5 -p -r1.34 ChangeLog
--- hal/powerpc/mbx/current/ChangeLog 11 Mar 2003 17:14:14 -0000 1.34
+++ hal/powerpc/mbx/current/ChangeLog 23 Mar 2003 16:08:27 -0000
@@ -1,5 +1,9 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * cdl/hal_powerpc_mbx.cdl: New option for setting processor type.
+
2003-03-11 Mark Salter <msalter at redhat dot com>
* src/redboot_linux_exec.c (do_exec): Call eth_drv_stop as necessary.
2003-03-07 Gary Thomas <gary at mlbassoc dot com>
Index: hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl,v
retrieving revision 1.16
diff -u -5 -p -r1.16 hal_powerpc_mbx.cdl
--- hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl 26 Nov 2002 13:48:18 -0000 1.16
+++ hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl 23 Mar 2003 13:06:44 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -64,10 +64,12 @@ cdl_package CYGPKG_HAL_POWERPC_MBX {
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGNUM_HAL_QUICC_SMC1
+
+ requires { CYGHWR_HAL_POWERPC_MPC8XX == "860" }
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_mbx.h>"
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.27
diff -u -5 -p -r1.27 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog 7 Mar 2003 02:34:57 -0000 1.27
+++ hal/powerpc/mpc8xx/current/ChangeLog 23 Mar 2003 16:10:01 -0000
@@ -1,5 +1,16 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/var_intr.c:
+ * include/var_intr.h: Clean up for new CDL (processor type) layout.
+
+ * src/var_misc.c:
+ * include/var_cache.h: Better processor/variant support.
+
+ * cdl/hal_powerpc_mpc8xx.cdl: Rearrange options to handle processor
+ type more flexibly.
+
2003-03-06 Gary Thomas <gary at mlbassoc dot com>
* src/var_misc.c: Can only reset CPM if not relying on a ROM monitor.
2003-03-05 Gary Thomas <gary at mlbassoc dot com>
Index: hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl,v
retrieving revision 1.8
diff -u -5 -p -r1.8 hal_powerpc_mpc8xx.cdl
--- hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl 15 Nov 2002 00:27:22 -0000 1.8
+++ hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl 23 Mar 2003 13:40:18 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -100,37 +100,19 @@ cdl_package CYGPKG_HAL_POWERPC_MPC8xx {
puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)"
puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 250000"
}
- cdl_component CYGPKG_HAL_POWERPC_MPC823 {
- display "PowerPC 823 microprocessor"
+ cdl_component CYGHWR_HAL_POWERPC_MPC8XX {
+ display "PowerPC 8xx microprocessor family"
+ flavor data
+ legal_values { "823" "850" "852T" "855T" "860" "860T" "862T" "862P" }
+ default_value "860"
implements CYGINT_HAL_POWERPC_VARIANT
description "
- The PowerPC 823 microprocessor. This is an embedded part that in
- addition to the PowerPC processor core has built in peripherals
- such as memory controllers, DMA controllers, serial ports and
- timers/counters."
- }
-
- cdl_component CYGPKG_HAL_POWERPC_MPC850 {
- display "PowerPC 850 microprocessor"
- implements CYGINT_HAL_POWERPC_VARIANT
- description "
- The PowerPC 850 microprocessor. This is an embedded part that in
- addition to the PowerPC processor core has built in peripherals
- such as memory controllers, DMA controllers, serial ports and
- timers/counters."
- }
-
- cdl_component CYGPKG_HAL_POWERPC_MPC860 {
- display "PowerPC 860 microprocessor"
- default_value 1
- implements CYGINT_HAL_POWERPC_VARIANT
- description "
- The PowerPC 860 microprocessor. This is an embedded part that in
- addition to the PowerPC processor core has built in peripherals
+ The PowerPC 8xx microprocessor family. These are embedded parts
+ that in addition to the PowerPC processor core have built in peripherals
such as memory controllers, DMA controllers, serial ports and
timers/counters."
cdl_option CYGHWR_HAL_POWERPC_FPU {
display "Variant FPU support"
Index: hal/powerpc/mpc8xx/current/include/var_cache.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_cache.h,v
retrieving revision 1.4
diff -u -5 -p -r1.4 var_cache.h
--- hal/powerpc/mpc8xx/current/include/var_cache.h 13 Nov 2002 21:05:26 -0000 1.4
+++ hal/powerpc/mpc8xx/current/include/var_cache.h 23 Mar 2003 15:28:30 -0000
@@ -9,10 +9,11 @@
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -65,33 +66,54 @@
//-----------------------------------------------------------------------------
// Cache dimensions - these vary between the 8xx sub-models
-#if defined(CYGPKG_HAL_POWERPC_MPC860)
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
+// Data cache
+#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
+#define HAL_DCACHE_WAYS 2 // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
+#define HAL_ICACHE_WAYS 2 // Associativity of the cache
+#endif // defined(CYGHWR_HAL_POWERPC_MPC862P)
+
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
// Data cache
#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 2 // Associativity of the cache
// Instruction cache
#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 2 // Associativity of the cache
-#endif // defined(CYGPKG_HAL_POWERPC_MPC860)
+#endif // defined(CYGHWR_HAL_POWERPC_MPC860)
-#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
// Data cache
#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 2 // Associativity of the cache
// Instruction cache
#define HAL_ICACHE_SIZE 2048 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 2 // Associativity of the cache
-#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
+#endif // defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
+
+#ifndef HAL_ICACHE_SIZE
+#error Missing cache definitions for this processor?
+#endif
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
//-----------------------------------------------------------------------------
Index: hal/powerpc/mpc8xx/current/include/var_intr.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_intr.h,v
retrieving revision 1.5
diff -u -5 -p -r1.5 var_intr.h
--- hal/powerpc/mpc8xx/current/include/var_intr.h 23 May 2002 23:04:27 -0000 1.5
+++ hal/powerpc/mpc8xx/current/include/var_intr.h 23 Mar 2003 12:46:16 -0000
@@ -9,10 +9,11 @@
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -41,11 +42,11 @@
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
-// Contributors:nickg, jskov, jlarmour, hmt
+// Contributors:nickg, jskov, jlarmour, hmt, gthomas
// Date: 2000-04-02
// Purpose: Variant interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock on the MPC8xx variant CPUs.
// Usage: Is included via the architecture interrupt header:
@@ -94,11 +95,11 @@
// These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()
#define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
-#ifdef CYGPKG_HAL_POWERPC_MPC860
+#ifdef CYGHWR_HAL_POWERPC_MPC8XX
// The MPC860 does not generate DSI and ISI: instead it goes to machine
// check, so that a software VM system can then call into vectors 0x300 or
// 0x400 if the address is truly invalid rather than merely not in the TLB
// right now. Shades of IBM wanting to port OS/MVS here!
// See pp 7-9/10 in "PowerQUICC - MPC860 User's Manual"
@@ -221,11 +222,11 @@
//--------------------------------------------------------------------------
// Interrupt controller access
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
-#ifdef CYGPKG_HAL_POWERPC_MPC860
+#ifdef CYGHWR_HAL_POWERPC_MPC8XX
static __inline__ void
cyg_hal_interrupt_mask ( cyg_uint32 vector )
{
switch (vector) {
@@ -679,22 +680,22 @@ cyg_hal_interrupt_set_level ( cyg_uint32
#endif
//--------------------------------------------------------------------------
// Interrupt arbiters
-#ifdef CYGPKG_HAL_POWERPC_MPC860
+#ifdef CYGHWR_HAL_POWERPC_MPC8XX
externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
-#endif // ifdef CYGPKG_HAL_POWERPC_MPC860
+#endif // ifdef CYGHWR_HAL_POWERPC_MPC8XX
//-----------------------------------------------------------------------------
// Symbols used by assembly code
#define CYGARC_VARIANT_DEFS \
DEFINE(CYGNUM_HAL_VECTOR_NMI, CYGNUM_HAL_VECTOR_NMI);
Index: hal/powerpc/mpc8xx/current/src/var_intr.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/src/var_intr.c,v
retrieving revision 1.7
diff -u -5 -p -r1.7 var_intr.c
--- hal/powerpc/mpc8xx/current/src/var_intr.c 23 May 2002 23:04:28 -0000 1.7
+++ hal/powerpc/mpc8xx/current/src/var_intr.c 23 Mar 2003 12:46:14 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -39,11 +40,11 @@
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
-// Contributors: jskov
+// Contributors: jskov, gthomas
// Date: 2000-02-11
// Purpose: PowerPC variant interrupt handlers
// Description: This file contains code to handle interrupt related issues
// on the PowerPC variant.
//
@@ -54,11 +55,10 @@
#include <pkgconf/hal.h>
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/hal_arbiter.h>
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-#ifdef CYGPKG_HAL_POWERPC_MPC860
// Since the interrupt sources do not have fixed vectors on the 860
// SIU, some arbitration is required.
// More than one interrupt source can be programmed to use the same
@@ -174,11 +174,10 @@ hal_arbitration_isr_cpm (CYG_ADDRWORD ve
return isr_ret;
}
return 0;
}
-#endif // ifdef CYGPKG_HAL_POWERPC_MPC860
externC void
hal_variant_IRQ_init(void)
{
#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
Index: hal/powerpc/mpc8xx/current/src/var_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/src/var_misc.c,v
retrieving revision 1.13
diff -u -5 -p -r1.13 var_misc.c
--- hal/powerpc/mpc8xx/current/src/var_misc.c 7 Mar 2003 02:34:57 -0000 1.13
+++ hal/powerpc/mpc8xx/current/src/var_misc.c 23 Mar 2003 15:30:41 -0000
@@ -7,11 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -105,24 +105,29 @@ hal_variant_idle_thread_action( cyg_uint
// is increased as resources are used and should be used for subsequent
// invocations.
//
// The MPC8xx CPUs do not have BATs. Fortunately we don't currently
// use the MMU, so we can simulate BATs by using the TLBs.
+
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
+#define NUM_TLBS 32
+#elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
+#define NUM_TLBS 8
+#else
+#error Missing TLB information for this platform
+#endif
+
int
cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys,
cyg_int32 size, cyg_uint8 flags)
{
cyg_uint32 epn, rpn, twc, ctr = 0;
- int max_tlbs;
-
-#if defined(CYGPKG_HAL_POWERPC_MPC860)
- // There are 32 TLBs.
- max_tlbs = 32;
-#elif defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
- // There are 8 TLBs.
- max_tlbs = 8;
-#endif
epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV;
rpn = ((phys & MI_RPN_RPNMASK)
| MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V);
if (flags & CYGARC_MEMDESC_CI)
@@ -131,11 +136,11 @@ cyg_hal_map_memory (int id,CYG_ADDRESS v
twc = MI_TWC_PS8MB | MI_TWC_V;
if (flags & CYGARC_MEMDESC_GUARDED)
twc |= MI_TWC_G;
// Ignore attempts to use more than max_tlbs.
- while (id < max_tlbs && size > 0) {
+ while (id < NUM_TLBS && size > 0) {
ctr = id << MI_CTR_INDX_SHIFT;
// Instruction TLB.
CYGARC_MTSPR (MI_TWC, twc);
CYGARC_MTSPR (MI_CTR, ctr);
@@ -168,32 +173,22 @@ cyg_hal_map_memory (int id,CYG_ADDRESS v
CYGARC_MTSPR (MD_CTR, ctr | CYGARC_REG_MD_CTR_CIDEF);
return id;
}
-
// Initialize MMU to a sane (NOP) state.
//
// Initialize TLBs with 0, Valid bits unset.
void
cyg_hal_clear_MMU (void)
{
cyg_uint32 ctr = 0;
int id;
- int max_tlbs;
-
-#if defined(CYGPKG_HAL_POWERPC_MPC860)
- // There are 32 TLBs.
- max_tlbs = 32;
-#elif defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
- // There are 8 TLBs.
- max_tlbs = 8;
-#endif
CYGARC_MTSPR (M_CASID, 0);
- for (id = 0; id < max_tlbs; id++) {
+ for (id = 0; id < NUM_TLBS; id++) {
ctr = id << MI_CTR_INDX_SHIFT;
// Instruction TLBs.
CYGARC_MTSPR (MI_TWC, 0);
CYGARC_MTSPR (MI_CTR, ctr);
Index: hal/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.31
diff -u -5 -p -r1.31 ChangeLog
--- hal/powerpc/quicc/current/ChangeLog 20 Mar 2003 13:09:54 -0000 1.31
+++ hal/powerpc/quicc/current/ChangeLog 23 Mar 2003 16:12:47 -0000
@@ -1,5 +1,19 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/quicc_smc1.c: Use new baud rate generator allocation functions.
+ Merge SMC and SCC output functions.
+
+ * src/cpm.c: Add new function to allocate and manage the baud rate
+ generators. Used by all serial drivers.
+
+ * include/ppc8xx.h: Some common definitions moved here from various
+ QUICC serial files.
+
+ * cdl/hal_powerpc_quicc.cdl: Add interface for SCC4 (not implemented
+ by any platform yet)
+
2003-03-20 Gary Thomas <gary at mlbassoc dot com>
* src/cpm.c (_mpc8xx_allocBd): Improve "best guess" for intial DPRAM
allocation to use a value which is likely not to conflict with old
versions of RedBoot.
Index: hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl,v
retrieving revision 1.9
diff -u -5 -p -r1.9 hal_powerpc_quicc.cdl
--- hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl 5 Mar 2003 17:15:43 -0000 1.9
+++ hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl 23 Mar 2003 13:13:38 -0000
@@ -98,16 +98,22 @@ cdl_package CYGPKG_HAL_QUICC {
display "SCC3 is available for serial I/O"
description "
Port SCC3 is available for serial I/O"
}
+ cdl_interface CYGNUM_HAL_QUICC_SCC4 {
+ display "SCC4 is available for serial I/O"
+ description "
+ Port SCC4 is available for serial I/O"
+ }
+
compile quicc_smc1.c cpm.c
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
- calculated CYGNUM_HAL_QUICC_SMC1+CYGNUM_HAL_QUICC_SMC2+CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3
+ calculated CYGNUM_HAL_QUICC_SMC1+CYGNUM_HAL_QUICC_SMC2+CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3+CYGNUM_HAL_QUICC_SCC4
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
Index: hal/powerpc/quicc/current/include/ppc8xx.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/include/ppc8xx.h,v
retrieving revision 1.13
diff -u -5 -p -r1.13 ppc8xx.h
--- hal/powerpc/quicc/current/include/ppc8xx.h 7 Mar 2003 02:34:57 -0000 1.13
+++ hal/powerpc/quicc/current/include/ppc8xx.h 22 Mar 2003 13:40:41 -0000
@@ -934,16 +934,20 @@ static inline EPPC *eppc_base(void)
: /* no inputs */ );
return retval;
}
+// Function used to reset [only once!] the CPM
+__externC void _mpc8xx_reset_cpm(void);
// Function used to allocate space in shared memory area
// typically used for buffer descriptors, etc.
-__externC void _mpc8xx_reset_cpm(void);
__externC unsigned short _mpc8xx_allocBd(int len);
+// Function used to manage the pool of baud rate generators
+__externC unsigned long *_mpc8xx_allocate_brg(int port);
+
#define QUICC_BD_BASE 0x2000 // Start of shared memory
#define QUICC_BD_END 0x3000 // End of shared memory
#endif /* __ASSEMBLER__ */
@@ -981,7 +985,55 @@ __externC unsigned short _mpc8xx_allocBd
#define QUICC_CPM_SCC2 0x0040
#define QUICC_CPM_SCC3 0x0080
#define QUICC_CPM_SMC1 0x0090
#define QUICC_CPM_SCC4 0x00C0
#define QUICC_CPM_SMC2 0x00D0
+
+// SMC Events (interrupts)
+#define QUICC_SMCE_BRK 0x10 // Break received
+#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
+#define QUICC_SMCE_TX 0x02 // Tx interrupt
+#define QUICC_SMCE_RX 0x01 // Rx interrupt
+
+// SMC Mode Register
+#define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length
+#define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
+#define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
+#define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
+#define QUICC_SMCMR_UART (2<<4) // UART mode
+#define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
+#define QUICC_SMCMR_REN (1<<0) // Enable receiver
+
+// SMC Commands
+#define QUICC_SMC_CMD_InitTxRx (0<<8)
+#define QUICC_SMC_CMD_InitTx (1<<8)
+#define QUICC_SMC_CMD_InitRx (2<<8)
+#define QUICC_SMC_CMD_StopTx (4<<8)
+#define QUICC_SMC_CMD_RestartTx (6<<8)
+#define QUICC_SMC_CMD_Reset 0x8000
+#define QUICC_SMC_CMD_Go 0x0001
+
+// SCC PSMR masks ....
+#define QUICC_SCC_PSMR_ASYNC 0x8000
+#define QUICC_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb)
+#define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8)
+#define QUICC_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled)
+#define QUICC_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high)
+#define QUICC_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high)
+
+// SCC DSR masks
+#define QUICC_SCC_DSR_FULL 0x7e7e
+#define QUICC_SCC_DSR_HALF 0x467e
+
+// SCC GSMR masks ...
+#define QUICC_SCC_GSMR_H_INIT 0x00000060
+#define QUICC_SCC_GSMR_L_INIT 0x00028004
+#define QUICC_SCC_GSMR_L_Tx 0x00000010
+#define QUICC_SCC_GSMR_L_Rx 0x00000020
+
+// SCC Events (interrupts)
+#define QUICC_SCCE_BRK 0x0040
+#define QUICC_SCCE_BSY 0x0004
+#define QUICC_SCCE_TX 0x0002
+#define QUICC_SCCE_RX 0x0001
#endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
Index: hal/powerpc/quicc/current/src/cpm.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/src/cpm.c,v
retrieving revision 1.3
diff -u -5 -p -r1.3 cpm.c
--- hal/powerpc/quicc/current/src/cpm.c 20 Mar 2003 13:09:54 -0000 1.3
+++ hal/powerpc/quicc/current/src/cpm.c 23 Mar 2003 13:03:38 -0000
@@ -54,13 +54,13 @@
//==========================================================================
#include <pkgconf/hal.h>
#include <pkgconf/hal_powerpc_quicc.h>
#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
#include <cyg/hal/hal_arch.h>
-#ifdef CYGPKG_HAL_POWERPC_MPC860
// eCos headers decribing PowerQUICC:
#include <cyg/hal/quicc/ppc8xx.h>
// Information about DPRAM usage
// This lets the CPM/DPRAM information be shared by all environments
@@ -101,15 +101,138 @@ _mpc8xx_allocBd(int len)
bd = *nextBd;
if ((bd < QUICC_BD_BASE) || (bd > QUICC_BD_END)) {
// Most likely not set up - make a guess :-(
bd = *nextBd = QUICC_BD_BASE+0x400;
}
+ CYG_ASSERT((len & 0x7) == 0, "BD length must be multiple of 8 bytes");
len = (len + 7) & ~7; // Multiple of 8 bytes
*nextBd += len;
+ CYG_ASSERT(*nextBd < QUICC_BD_END, "Out of buffer descriptors!");
if (*nextBd >= QUICC_BD_END) {
*nextBd = QUICC_BD_BASE;
}
return bd;
}
-#endif // CYGPKG_HAL_POWERPC_MPC860
+#define BRG_MAX 4
+#define BRG_UNAVAIL -1
+#define BRG_FREE -2
+static unsigned long *brg[BRG_MAX]; // Available generators
+static int alloc[BRG_MAX]; // Which port is assigned where
+ // -1 indicates unavailable
+ // -2 indicates free
+ // xx indicates port assignment
+
+static void
+_mpc8xx_mark_brg(int port, int brgnum)
+{
+ if (brgnum >= BRG_MAX) {
+ return; // Invalid selection
+ }
+ if (alloc[brgnum] == BRG_FREE) {
+ // Allocation unknown
+ alloc[brgnum] = port;
+ }
+}
+
+unsigned long *
+_mpc8xx_allocate_brg(int port)
+{
+ EPPC *eppc = eppc_base();
+ static int init = 0;
+ int brgnum;
+
+ if (!init) {
+ // Set up available pool
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
+ // The 852T variant only has BRG3/BRG4
+ alloc[0] = BRG_UNAVAIL;
+ alloc[1] = BRG_UNAVAIL;
+#else
+ brg[0] = (unsigned long *)&eppc->brgc1; alloc[0] = BRG_FREE;
+ brg[1] = (unsigned long *)&eppc->brgc2; alloc[1] = BRG_FREE;
+#endif
+ brg[2] = (unsigned long *)&eppc->brgc3; alloc[2] = BRG_FREE;
+ brg[3] = (unsigned long *)&eppc->brgc4; alloc[3] = BRG_FREE;
+#if !defined(CYGSEM_HAL_ROM_MONITOR)
+ // Figure out how hardware was set by previous ROM monitor
+#if CYGNUM_HAL_QUICC_SMC1 > 0
+ _mpc8xx_mark_brg(QUICC_CPM_SMC1, (eppc->si_simode >> 12) & 0x07);
+#endif
+#if CYGNUM_HAL_QUICC_SMC2 > 0
+ _mpc8xx_mark_brg(QUICC_CPM_SMC2, (eppc->si_simode >> 28) & 0x07);
+#endif
+#if CYGNUM_HAL_QUICC_SCC1 > 0
+ _mpc8xx_mark_brg(QUICC_CPM_SCC1, (eppc->si_sicr >> 0) & 0x07);
+#endif
+#if CYGNUM_HAL_QUICC_SCC2 > 0
+ _mpc8xx_mark_brg(QUICC_CPM_SCC2, (eppc->si_sicr >> 8) & 0x07);
+#endif
+#if CYGNUM_HAL_QUICC_SCC3 > 0
+ _mpc8xx_mark_brg(QUICC_CPM_SCC3, (eppc->si_sicr >> 16) & 0x07);
+#endif
+#if CYGNUM_HAL_QUICC_SCC4 > 0
+ _mpc8xx_mark_brg(QUICC_CPM_SCC4, (eppc->si_sicr >> 24) & 0x07);
+#endif
+#endif
+ init = 1;
+ }
+ // Find a free generator (or if port has already been assigned)
+ for (brgnum = 0; brgnum < BRG_MAX; brgnum++) {
+ if (alloc[brgnum] >= 0) {
+ // See if it is for this port
+ if (alloc[brgnum] == port) {
+ // It is - just reuse it (already set up)
+ return brg[brgnum];
+ }
+ }
+ }
+ // Not currently assigned, try and find a free one
+ for (brgnum = 0; brgnum < BRG_MAX; brgnum++) {
+ if (alloc[brgnum] == BRG_FREE) {
+ // Allocate to this port.
+ alloc[brgnum] = port;
+ break;
+ }
+ }
+ CYG_ASSERT(brgnum < BRG_MAX, "Out of baud rate generators!");
+ // If no generator found - punt!
+ if (brgnum == BRG_MAX) {
+ brgnum = BRG_MAX-1;
+ }
+ // Set up clock routing for new assignment
+ switch (port) {
+#if CYGNUM_HAL_QUICC_SMC1 > 0
+ case QUICC_CPM_SMC1:
+ eppc->si_simode = (eppc->si_simode & ~(0x07<<12)) | (brgnum<<12);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SMC2 > 0
+ case QUICC_CPM_SMC2:
+ eppc->si_simode = (eppc->si_simode & ~(0x07<<28)) | (brgnum<<28);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SCC1 > 0
+ case QUICC_CPM_SCC1:
+ eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<0)) | (((brgnum<<3)|(brgnum<<0))<<0);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SCC2 > 0
+ case QUICC_CPM_SCC2:
+ eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<8)) | (((brgnum<<3)|(brgnum<<0))<<8);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SCC3 > 0
+ case QUICC_CPM_SCC3:
+ eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<16)) | (((brgnum<<3)|(brgnum<<0))<<16);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SCC4 > 0
+ case QUICC_CPM_SCC4:
+ eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<24)) | (((brgnum<<3)|(brgnum<<0))<<24);
+ break;
+#endif
+ }
+ return brg[brgnum];
+}
+
// EOF cpm.c
Index: hal/powerpc/quicc/current/src/quicc_smc1.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c,v
retrieving revision 1.25
diff -u -5 -p -r1.25 quicc_smc1.c
--- hal/powerpc/quicc/current/src/quicc_smc1.c 18 Mar 2003 14:03:27 -0000 1.25
+++ hal/powerpc/quicc/current/src/quicc_smc1.c 23 Mar 2003 16:00:48 -0000
@@ -59,12 +59,10 @@
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_arch.h>
-#ifdef CYGPKG_HAL_POWERPC_MPC860
-
// eCos headers decribing PowerQUICC:
#include <cyg/hal/quicc/ppc8xx.h>
#include <cyg/hal/quicc/quicc_smc1.h>
@@ -89,10 +87,11 @@ struct port_info {
int pram; // [Pointer] to PRAM data
int regs; // [Pointer] to control registers
volatile struct cp_bufdesc *next_rxbd;
int irq; // Interrupt state
int init; // Has port been initialized?
+ volatile unsigned long *brg; // Baud rate generator
};
static struct port_info ports[] = {
#if CYGNUM_HAL_QUICC_SMC1 > 0
{ 1, 4, CYGNUM_HAL_INTERRUPT_CPM_SMC1, 1000,
@@ -124,16 +123,10 @@ static struct port_info ports[] = {
(int)&((EPPC *)0)->scc_regs[2]
},
#endif
};
-// SMC Events (interrupts)
-#define QUICC_SMCE_BRK 0x10 // Break received
-#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
-#define QUICC_SMCE_TX 0x02 // Tx interrupt
-#define QUICC_SMCE_RX 0x01 // Rx interrupt
-
/*
* Initialize SMCX as a uart.
*
* Comments below reference Motorola's "MPC860 User Manual".
* The basic initialization steps are from Section 16.15.8
@@ -162,18 +155,10 @@ cyg_hal_smcx_init_channel(struct port_in
* (Table 16-39)
*/
eppc->pip_pbpar |= 0xc0;
eppc->pip_pbdir &= ~0xc0;
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
-
- /*
- * NMSI mode, BRG1 to SMC1
- * (Section 16.12.5.2)
- */
- eppc->si_simode = 0;
break;
#endif
#if CYGNUM_HAL_QUICC_SMC2 > 0
case QUICC_CPM_SMC2:
/*
@@ -183,22 +168,21 @@ cyg_hal_smcx_init_channel(struct port_in
*/
eppc->pio_papar |= 0xc0;
eppc->pio_padir &= ~0xc0;
eppc->pio_paodr &= ~0xc0;
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
-
- /*
- * NMSI mode, BRG1 to SMC2
- * (Section 16.12.5.2)
- */
- eppc->si_simode = 0x00000000;
break;
#endif
}
+ // Set up baud rate generator. These are allocated from a
+ // pool, based on the port number and type. The allocator
+ // will arrange to have the selected baud rate clock steered
+ // to this device.
+ info->brg = _mpc8xx_allocate_brg(port);
+ *(info->brg) = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
@@ -286,11 +270,11 @@ cyg_hal_smcx_init_channel(struct port_in
#ifdef CYGDBG_DIAG_BUF
extern int enable_diag_uart;
#endif // CYGDBG_DIAG_BUF
static void
-cyg_hal_smcx_putc(void* __ch_data, cyg_uint8 ch)
+cyg_hal_sxx_putc(void* __ch_data, cyg_uint8 ch)
{
volatile struct cp_bufdesc *bd, *first;
EPPC *eppc = eppc_base();
struct port_info *info = (struct port_info *)__ch_data;
volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
@@ -422,17 +406,17 @@ cyg_hal_sxx_getc(void* __ch_data)
return ch;
}
static void
-cyg_hal_smcx_write(void* __ch_data, const cyg_uint8* __buf,
+cyg_hal_sxx_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
- cyg_hal_smcx_putc(__ch_data, *__buf++);
+ cyg_hal_sxx_putc(__ch_data, *__buf++);
CYGARC_HAL_RESTORE_GP();
}
/*
@@ -606,17 +590,10 @@ cyg_hal_sccx_init_channel(struct port_in
/* RTS on PortB.19 */
eppc->pip_pbpar |= 0x1000;
eppc->pip_pbdir |= 0x1000;
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
-
- /*
- * NMSI mode, BRG2 to SCC1
- */
- eppc->si_sicr |= (1<<3)|(1<<0);
break;
#endif
#if CYGNUM_HAL_QUICC_SCC2 > 0
case QUICC_CPM_SCC2:
#error FIXME
@@ -631,17 +608,10 @@ cyg_hal_sccx_init_channel(struct port_in
/* RTS on PortB.19 */
eppc->pip_pbpar |= 0x2000;
eppc->pip_pbdir |= 0x2000;
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
-
- /*
- * NMSI mode, BRG2 to SCC2
- */
- eppc->si_sicr |= (1<<11)|(1<<8);
break;
#endif
#if CYGNUM_HAL_QUICC_SCC3 > 0
case QUICC_CPM_SCC3:
#if 0
@@ -656,22 +626,21 @@ cyg_hal_sccx_init_channel(struct port_in
/* RxD/TxD on PortB.24/25 */
eppc->pip_pbpar |= 0x00C0;
eppc->pip_pbdir |= 0x00C0;
eppc->pip_pbodr &= ~0x00C0;
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc4 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
-
- /*
- * NMSI mode, BRG4 to SCC3
- */
- eppc->si_sicr &= ~(0xFF << 16);
- eppc->si_sicr |= (3<<19)|(3<<16);
break;
#endif
}
+ // Set up baud rate generator. These are allocated from a
+ // pool, based on the port number and type. The allocator
+ // will arrange to have the selected baud rate clock steered
+ // to this device.
+ info->brg = _mpc8xx_allocate_brg(port);
+ *(info->brg) = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
/*
* Set pointers to buffer descriptors.
*/
memset((void *)uart_pram, 0xFF, 0x100);
uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
@@ -752,61 +721,10 @@ cyg_hal_sccx_init_channel(struct port_in
regs->scc_gsmr_l |= 0x30; // Enable Rx, Tx
info->irq = 0;
}
-static void
-cyg_hal_sccx_putc(void* __ch_data, cyg_uint8 ch)
-{
- volatile struct cp_bufdesc *bd, *first;
- EPPC *eppc = eppc_base();
- struct port_info *info = (struct port_info *)__ch_data;
- volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram);
- CYGARC_HAL_SAVE_GP();
-
- /* tx buffer descriptor */
- bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr);
-
- // Scan for a free buffer
- first = bd;
- while (bd->ctrl & QUICC_BD_CTL_Ready) {
- if (bd->ctrl & QUICC_BD_CTL_Wrap) {
- bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
- } else {
- bd++;
- }
- if (bd == first) break;
- }
-
- while (bd->ctrl & QUICC_BD_CTL_Ready) ; // Wait for buffer free
- if (bd->ctrl & QUICC_BD_CTL_Int) {
- // This buffer has just completed interrupt output. Reset bits
- bd->ctrl &= ~QUICC_BD_CTL_Int;
- bd->length = 0;
- }
-
- bd->length = 0;
- bd->buffer[bd->length++] = ch;
- bd->ctrl |= QUICC_BD_CTL_Ready;
-
- while (bd->ctrl & QUICC_BD_CTL_Ready) ; // Wait until buffer free
-
- CYGARC_HAL_RESTORE_GP();
-}
-
-static void
-cyg_hal_sccx_write(void* __ch_data, const cyg_uint8* __buf,
- cyg_uint32 __len)
-{
- CYGARC_HAL_SAVE_GP();
-
- while(__len-- > 0)
- cyg_hal_sccx_putc(__ch_data, *__buf++);
-
- CYGARC_HAL_RESTORE_GP();
-}
-
static int
cyg_hal_sccx_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
EPPC *eppc = eppc_base();
@@ -875,13 +793,13 @@ cyg_hal_plf_serial_init(void)
// Set up SMC1
cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC1);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smcx_write);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smcx_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
@@ -891,13 +809,13 @@ cyg_hal_plf_serial_init(void)
// Set up SMC2
cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC2);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smcx_write);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smcx_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
@@ -907,13 +825,13 @@ cyg_hal_plf_serial_init(void)
// Set up SCC1
cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC1);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
@@ -923,13 +841,13 @@ cyg_hal_plf_serial_init(void)
// Set up SCC2
cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC2);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
@@ -939,13 +857,13 @@ cyg_hal_plf_serial_init(void)
// Set up SCC3
cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC3);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
@@ -953,7 +871,6 @@ cyg_hal_plf_serial_init(void)
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
-#endif // CYGPKG_HAL_POWERPC_MPC860
// EOF quicc_smc1.c
Index: hal/powerpc/ts1000/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ts1000/current/ChangeLog,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ChangeLog
--- hal/powerpc/ts1000/current/ChangeLog 2 Dec 2002 20:42:58 -0000 1.7
+++ hal/powerpc/ts1000/current/ChangeLog 23 Mar 2003 16:13:05 -0000
@@ -1,5 +1,9 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * cdl/hal_powerpc_ts1000.cdl: New CDL for setting processor type.
+
2002-12-02 Gary Thomas <gthomas at ecoscentric dot com>
* include/plf_intr.h: Use MPC8xx variant RESET support.
2002-11-26 Gary Thomas <gthomas at ecoscentric dot com>
Index: hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl,v
retrieving revision 1.4
diff -u -5 -p -r1.4 hal_powerpc_ts1000.cdl
--- hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl 26 Nov 2002 13:48:19 -0000 1.4
+++ hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl 23 Mar 2003 15:02:51 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -65,15 +65,17 @@ cdl_package CYGPKG_HAL_POWERPC_TS1000 {
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGNUM_HAL_QUICC_SMC1
+ requires { CYGHWR_HAL_POWERPC_MPC8XX == "855T" }
+
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_ts1000.h>"
- puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 855\""
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 855T\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Allied Telesyn TS1000\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
}
cdl_component CYG_HAL_STARTUP {
Index: hal/powerpc/viper/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/ChangeLog,v
retrieving revision 1.23
diff -u -5 -p -r1.23 ChangeLog
--- hal/powerpc/viper/current/ChangeLog 11 Mar 2003 17:14:15 -0000 1.23
+++ hal/powerpc/viper/current/ChangeLog 23 Mar 2003 16:13:37 -0000
@@ -1,5 +1,9 @@
+2003-03-23 Gary Thomas <gary at mlbassoc dot com>
+
+ * cdl/hal_powerpc_viper.cdl: New CDL for setting processor type.
+
2003-03-11 Mark Salter <msalter at redhat dot com>
* src/redboot_linux_exec.c (do_exec): Call eth_drv_stop as necessary.
2003-03-07 Gary Thomas <gary at mlbassoc dot com>
Index: hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl,v
retrieving revision 1.13
diff -u -5 -p -r1.13 hal_powerpc_viper.cdl
--- hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl 4 Mar 2003 16:16:02 -0000 1.13
+++ hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl 23 Mar 2003 16:13:36 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -65,10 +65,12 @@ cdl_package CYGPKG_HAL_POWERPC_VIPER {
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGNUM_HAL_QUICC_SMC1
implements CYGNUM_HAL_QUICC_SCC1
+
+ requires { (CYGHWR_HAL_POWERPC_MPC8XX == "860T") || (CYGHWR_HAL_POWERPC_MPC8XX == "862P") }
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_viper.h>"
Index: hal/powerpc/viper/current/misc/redboot_ROMRAM.ecm
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/misc/redboot_ROMRAM.ecm,v
retrieving revision 1.3
diff -u -5 -p -r1.3 redboot_ROMRAM.ecm
--- hal/powerpc/viper/current/misc/redboot_ROMRAM.ecm 31 Jul 2002 14:16:36 -0000 1.3
+++ hal/powerpc/viper/current/misc/redboot_ROMRAM.ecm 23 Mar 2003 16:15:59 -0000
@@ -15,18 +15,20 @@ cdl_configuration eCos {
package -hardware CYGPKG_HAL_POWERPC_MPC8xx current ;
package -hardware CYGPKG_HAL_POWERPC_VIPER current ;
package -hardware CYGPKG_HAL_QUICC current ;
package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC current ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_FEC current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_VIPER current ;
package -hardware CYGPKG_DEVS_FLASH_VIPER current ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_ISOINFRA current ;
package -template CYGPKG_LIBC_STRING current ;
package -template CYGPKG_NS_DNS current ;
+ package -template CYGPKG_CRC current ;
package CYGPKG_IO_FLASH current ;
package CYGPKG_IO_ETH_DRIVERS current ;
package CYGPKG_COMPRESS_ZLIB current ;
package CYGPKG_MEMALLOC current ;
};
@@ -51,10 +53,14 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_
inferred_value 1
};
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
+};
+
+cdl_component CYGHWR_HAL_POWERPC_MPC8XX {
+ inferred_value 860T
};
cdl_component CYG_HAL_STARTUP {
user_value ROMRAM
};
--
------------------------------------------------------------
Gary Thomas |
MLB Associates | Consulting for the
+1 (970) 229-1963 | Embedded world
http://www.mlbassoc.com/ |
email: <gary at mlbassoc dot com> |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------