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Re: Interrupt stacking issues


Le 19/07/2012 18:28, Alan Bowman a écrit :

Wow, that's a lot of detail to sort through - I'm going to have to think about that for a bit. On the face of it, we may well have that problem. However, I haven't worked out how that matches our symptoms. I thought that all of the ISRs (and the PendSV/DSR) could only run once at a time. If an ISR triggers the PendSV, it will be off the stack by the time PendSV runs. It can then pre-empt the PendSV exception (so both will appear on the stack at once), but only once.
Your situation may be related to nested interrupts. I didn't look at this potential issue since I didn't suffered from it :-)

For instance if you setup the UART interrupt priority at a lower value than what is used by eCos to disable interrupts (default is 8 from what I recall for the LPC17XX), then an UART interrupt can be triggered even when you think you have disabled interrupts! If you have different UART with different interrupt priority levels and all have a value < 8 (if 8 is the value setup by eCos in your case), then the ISR for an UART can be triggered even if an ISR of another UART with a lower priority is running and this could explain what you get.

The PendSV exception bit may well be set again, but it will have to
wait for the first one to finish (and presumably be off the stack)
before running again.  Lots of different ISRs could all pre-empt each
other, but I don't _think_ that's what's happening.

Did you see any issues like this when you were investigating, or was
unnecessary ISR/DSR calls the key issue?
My problem was unnecessary ISR/DSR calls, and since my target clocks slowly, I didn't want to waste any time or power in superfluous processing. If the problem is related to interrupt priority, it's a different story but my guess is that you will also be interested in the pending bit problem because if you clock at 8MHz you may have constraints similar to the ones I have.
Bernard



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