[ECOS] [eCos-discuss] Cortex-M arch questions

[Mike DeSimone <desimone at arlut dot utexas dot edu>]

I'm trying to work through what is in the Cortex-M architecture  
already.  I've run into some things which are confusing me.

In packages/hal/cortexm/arch/current/include/hal_intr.h is the line:

#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_SYS_TICK

The first Cortex-M supported, the STM32, doesn't have a real-time  
clock peripheral, just the SysTick peripheral that comes with the  
Cortex-M core, but the one I'm porting to, the Atmel ATSAM3U, has an  
RTC distinct from the SysTick peripheral.  Normally, I'd name its  
interrupt CYGNUM_HAL_INTERRUPT_RTC, but that's already defined in the  
architecture, so I'm wondering if CYGNUM_HAL_INTERRUPT_RTC has special  
meaning within eCos?  Is it required to be present?  And if so, what  
are its requirements (i.e. which "RTC" would be better to label as the  
RTC?)

Also, I think I found a bug elsewhere in the STM32 architecture  
files.  Is there a Bugzilla or equivalent for eCos?

Finally, I saw some discussion of moving eCos to Subversion in the  
archives.  Did anything come of this? Subversion would be easier for  
me to interface with than CVS; right now, I've got the CVS checkout  
superimposed on a Subversion tree used for local development.

Thanks!


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