This is the mail archive of the
ecos-discuss@sourceware.org
mailing list for the eCos project.
Re: DSR stops running after heavy interrupts. Spurious Interrupt!
"Joe Porthouse" <jporthouse@toptech.com> writes:
> Ok, found the source of the Spurious Interrupts, (your really going to love
> this one).
[...]
> Clearing this interrupt occurs if you read from the Receiver FIFO, set the
> FCR[RESETRF] bit or A NEW START BIT IS RECEIVED!!!
>
> So if the RX FIFO is below the trigger point and a timeout occurs an IRQ
> request is generated, but if a new start bit is detected the IRQ request is
> then immediately cleared. :(
>
> Wow an interrupt that can clear its own IRQ request before service occurs!!!
> That would surely cause a Spurious Interrupt.
Sounds like yet another piece of broken hardware design from Intel, --
they failed to deliver reasonable RS232 implementation at the early
days of PC, and still fail to do it right in 20 years :(
-- Sergei.
--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss