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Re: Re: DSR Scheduling Problem

From: Andrew Lunn <andrew at lunn dot ch>
To: Daniel N?ri <daniel dot neri at sigicom dot se>
Cc: ecos-discuss at sources dot redhat dot com
Date: Tue, 17 Jan 2006 10:43:34 +0100
Subject: Re: [ECOS] Re: DSR Scheduling Problem
References: <dq9mma$d9l$1@sea.gmane.org> <NEBBKHCFDGIGIJEHDJFCCEMICIAB.pderocco@ix.netcom.com> <dq9rq5$pkn$1@sea.gmane.org> <87vewklg60.fsf@ebbot.hq.sigicom.net>

> > That's insane. Nobody with a clue would write software like that.
> 
> Actually, the generic 16x5x serial driver in eCos works exactly like
> that.
> 
> > When you get a TX interrupt you write data to the tx FIFO until it's
> > full.
> 
> Yep. I've made a somewhat quick-and-dirty fix that is attached below.

Would somebody like to make a clean fix for this. I will then commit
it.

        Thanks
                Andrew               

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References:
- Re: DSR Scheduling Problem
  - From: Grant Edwards
- RE: Re: DSR Scheduling Problem
  - From: Paul D. DeRocco
- Re: DSR Scheduling Problem
  - From: Grant Edwards
- Re: DSR Scheduling Problem
  - From: Daniel Néri

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