[ECOS] Re: ISR not causing an DSR in some rare conditions

[Sergei Organov <osv at javad dot com>]

"Stefan Sommerfeld" <sommerfeld@mikrom.de> writes:
[...]
>>> No. The interrupts will not be disabled at any time. The interrupt from
>>> this source will only be acknowledged in the isr function.
>>>
>>> The functionality is simple. A hardware unit will be started and
>>> reports the finish with an interrupt. I have made a counter on
>>> hardware unit start, isr and dsr. After this long-run test, the dsr
>>> counter is one less than the other counters.
>>
[...]
>> Thus, you need to increment your test counter by the value of 'count'
>> argument in the DSR handler, do you?
>
> No... you don't understand.

Well, maybe, but that's how I read your:

>>> No. The interrupts will not be disabled at any time. The interrupt from
>>> this source will only be acknowledged in the isr function.

If interrupts are not disabled, and interrupt is acked in isr function
as you wrote above, then more than one could happen while no dsr is run
yet.

> The dsr count of this particular irq cannot be other than 1.

Well, seems I indeed misunderstand, but did you *actually* check it
isn't? Ah, well, from your other reply I see you didn't, though I'd
check anyway as "cannot" and "doesn't indeed happen" are surprisingly
different, at least in my experience.

> The hardware unit causes only one irq some time after it was
> started. If ecos does not call the dsr routine, the hardware unit will
> not be started again and so no more irq's will be caused.

Do you say that it's DSR that restarts the hardware unit? Seems so
though you didn't tell it to us before.

After DSR is missed is the entire system operational? I mean is the rest
of the system running OK (including ISRs/DSRs from other sources,
e.g., timer) after the DSR is missing? If so, then it looks like some
race somewhere, either in your code or in the eCos, or entirely
independent bug that just happens to break this thing.

BTW, if it runs on ARM, do you use FIQ? I think I know at least 2 bugs
in the ARM HAL, one of which is with FIQ handling (and another one being
in the context switch), but chances are very low they show themselves
the way you see.

-- Sergei.


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