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Re: PowerPC cyg_hal_default_exception_vsr Bug?


On Thu, 2005-10-27 at 19:11 -0400, Jeffrey R. Szczepanski wrote:
> In the PowerPC architecture port of the routine 
> cyg_hal_default_exception_vsr, (hal/powerpc/arch/src/vectors.S) there 
> appears 3 stores of context to the stack before the MMU context is restored. 
> Does this bother anybody else? I believe that is a bug since the stores will 
> not necessarly occur with the proper cache-ability control since the MMU is 
> still off at entry to the exception handler. ie: If MMU is on and Caches are 
> on before the exception (likely!) any accesses to memory prior to 
> re-enabling the MMU are potentially done "incorrectly" relative to cache 
> control status. I believe the MMU operation must be done first, always!
> 
> To be more specific to the code itself, I believe the follows lines:
> 
>         # Enable MMU & interrupt/FPU environment (as configured)
>         lwi     r3,CYG_MSR
>         sync
>         mtmsr   r3
>         sync
> 
> should specifically appear before these lines:
> 
>         # First, save away some registers
>         stw     r3,CYGARC_PPCREG_VECTOR(sp)    # stash vector
>         stw     r4,CYGARC_PPCREG_CR(sp)        # stash CR
>         stw     r5,CYGARC_PPCREG_LR(sp)        # stash LR
> 
> Does anybody else agree, or am I missing something here!?

On all PowerPC platforms, except for the 40x, cache control is
independent of MMU settings.  The only way I can see that you
would have a problem is if you happened to have a stack in an
area of memory which was purposefully cache disabled using the
MMU.  This would certainly not be normal (nor even desirable IMO)

Perhaps you care to explain how the cache-ability might change
with the MMU setting (other than what I've just outlined)?

-- 
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------


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