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ARM port architecture questions
- From: "Patrick Doyle" <wpd at delcomsys dot com>
- To: "eCos" <ecos-discuss at sources dot redhat dot com>
- Date: Mon, 25 Nov 2002 11:14:15 -0500
- Subject: [ECOS] ARM port architecture questions
I have a couple of questions about the eCos port to the ARM architecture.
As I wander through vectors.S, I noticed a few things...
1) It appears that the 8 (well, 7 actually, plus one undefined) exception
vectors at address 0 .. 0x20 are duplicated at address 0x20..0x40. Am I
interpreting this correctly? Why is this?
2) It also appears that vectors.S his hard wired to expect the exception
vectors at address 0. I can understand why this is the case, since the
processor is hard wired to find its vectors at this address, but some
processors offer a means to change the default vector location to high
memory. Or, in my case, I might have a ROM at address 0 that branches to a
RAM vector table. (Yes, I know this is more expensive than having RAM at
address 0 and less correct/elegant than using the MMU to map RAM to address
0, but it's what I have today). How difficult would it be for me to add a
CDL option to allow the vectors to be remapped to an arbitrary (correctly
aligned) address? Am I setting myself up for failure if I attempt this?
--wpd
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