[ECOS] GDB support in ARM thumb mode

[Rich LeGrand <richintervideo at yahoo dot com>]

Hi all,
I noticed something in vectors.S (for ARM) that has been causing us some
problems.  Around line 584:

        // switch to pre-exception mode to get banked regs
        mov     r0,sp                   // r0 survives mode switch
        mrs     r2,cpsr                 // Save current psr for return
        orr     r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
        msr     cpsr,r1

Here, r1 contains the SPSR.  If we set a debugging breakpoint in thumb code and
enter the above code through the illegal instruction exception, the msr
instruction above will necessarily set the T bit, which is bad.  Masking the
mode bits such as:

        // switch to pre-exception mode to get banked regs
        mov     r0,sp                   // r0 survives mode switch
        mrs     r2,cpsr                 // Save current psr for return

        bic     r4,r2,#CPSR_MODE_BITS   // clear mode bits
        and     r1,r1,#CPSR_MODE_BITS   // isolate mode bits

        orr     r1,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE 
        msr     cpsr,r1 

seems to fix this issue.  That is, when attaching GDB to Redboot (running in
thumb) before the change, GDB would hang.  After the change, we can attach GDB
and load the program, but we notice problems later when we encounter
breakpoints that we set.  

Has there been much testing with debugging ARM thumb code lately?  (since
vectors.s was changed significantly 3 months ago.)

Any information would be greatly appreciated.

Thanks!

Rich LeGrand


__________________________________________________
Do You Yahoo!?
Yahoo! Finance - Get real-time stock quotes
http://finance.yahoo.com

-- 
Before posting, please read the FAQ: http://sources.redhat.com/fom/ecos
and search the list archive: http://sources.redhat.com/ml/ecos-discuss