This is the mail archive of the ecos-discuss@sources.redhat.com mailing list for the eCos project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

FIFO support in CDL for 16x5x



Hi,
	Attached is a patch to add basic FIFO RX support to the 16x5x
driver via CDL, it just adds an option to the 16x5x driver to set a FIFO
RX threshold of 1,4,8, or 14 bytes, 

The default case is to use the single byte so it shouldn't affect any
existing systems..

Dave.

-- 
      David Airlie, Software Engineer, Parthus Technologies plc.,
       Mary Rosse Centre, National Tech Park, Limerick, Ireland.
   t: +353-61-508116 / f: +353-61-508101 / David.Airlie@parthus.com
? devs/serial/generic/16x5x/current/src/ser_16x5x.c_dave
? devs/serial/generic/16x5x/current/src/ser_16x5x.c_dave_do_stuff_in_ISR
? devs/serial/generic/16x5x/current/src/ser_16x5x.c_isrversion
Index: devs/serial/generic/16x5x/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/generic/16x5x/current/ChangeLog,v
retrieving revision 1.4
diff -u -r1.4 ChangeLog
--- ChangeLog	2001/01/26 08:15:27	1.4
+++ ChangeLog	2001/02/15 20:31:13
@@ -1,3 +1,10 @@
+2001-02-15  Dave Airlie <airlied@parthus.com>
+        * src/ser_16x5x.c (serial_config_port): Add support for setting
+        a FIFO RX Threshold via CDL
+
+        * cdl/ser_generic_16x5x.cdl: Add support for setting a FIFO
+          RX threshold via CDL
+
 2001-01-24  Dave Airlie  <airlied@parthus.com>
 
 	* src/ser_16x5x.c (pc_serial_DSR): Allow RX timeouts to be interpreted
Index: devs/serial/generic/16x5x/current/cdl/ser_generic_16x5x.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/generic/16x5x/current/cdl/ser_generic_16x5x.cdl,v
retrieving revision 1.1
diff -u -r1.1 ser_generic_16x5x.cdl
--- ser_generic_16x5x.cdl	2000/09/19 05:53:53	1.1
+++ ser_generic_16x5x.cdl	2001/02/15 20:31:13
@@ -67,9 +67,27 @@
         puts $::cdl_header "#include CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG";
     }
 
+    cdl_component CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_OPTIONS {
+	display "16x5x FIFO Options"
+	flavor none
+	default_value 1
+	description   "
+	    Options to configure the FIFO on a 16550 variant."
+	
+	cdl_option CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD {
+	display "Threshold for RX interrupt on 16550 FIFO (both channels)"
+	flavor data
+	legal_values { 14 8 4 1 }
+	default_value 1
+	description "
+	     This options configures the threshold value at which the RX interrupt occurs when a FIFO is used. (16550 only), this may be after 1, 4, 8 or 14 characters."
+	}
+    }		
+	     
     cdl_component CYGPKG_IO_SERIAL_GENERIC_16X5X_OPTIONS {
         display "Serial device driver build options"
         flavor  none
+
         description   "
 	    Package specific build options including control over
 	    compiler flags used only in building this package,
Index: devs/serial/generic/16x5x/current/src/ser_16x5x.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c,v
retrieving revision 1.4
diff -u -r1.4 ser_16x5x.c
--- ser_16x5x.c	2001/01/26 08:15:27	1.4
+++ ser_16x5x.c	2001/02/15 20:31:13
@@ -209,6 +209,7 @@
     cyg_addrword_t base = ser_chan->base;
     unsigned short baud_divisor = select_baud[new_config->baud];
     unsigned char _lcr, _ier;
+    unsigned char _fifo_thresh, _fcr_thresh=0;
     if (baud_divisor == 0) return false;  // Invalid configuration
 
     // Disable port interrupts while changing hardware
@@ -223,7 +224,22 @@
     HAL_WRITE_UINT8(base+REG_ldl, baud_divisor & 0xFF);
     HAL_WRITE_UINT8(base+REG_lcr, _lcr);
     if (init) {
-        HAL_WRITE_UINT8(base+REG_fcr, FCR_FE|FCR_CRF|FCR_CTF|FCR_RT1);  // Enable and clear FIFO
+#if CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_OPTIONS
+      _fifo_thresh=CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD;
+      switch(_fifo_thresh)
+	{
+	case 1:
+	  _fcr_thresh=FCR_RT1; break;
+	case 4:
+	  _fcr_thresh=FCR_RT4; break;
+	case 8:
+	  _fcr_thresh=FCR_RT8; break;
+	case 14:
+	  _fcr_thresh=FCR_RT14; break;
+	}
+#endif
+      _fcr_thresh|=FCR_FE|FCR_CRF|FCR_CTF;
+        HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh);  // Enable and clear FIFO
         if (chan->out_cbuf.len != 0) {
             _ier = IER_RCV;
         } else {

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]