Re: [ECOS] nested interrupts

["Xavier Wang" <xavierwang at ms19 dot url dot com dot tw>]

Thanks, Jesper.


> >>>>> "Xavier" == Xavier Wang <xavierwang@ms19.url.com.tw> writes:
> 
> Xavier> I got confused about nested interrupts. In
> Xavier> http://sources.redhat.com/ecos/docs-latest/porting/hal-interrupts.html
> Xavier> it seems that interrupts are disabled in ISRs, but enabled in
> Xavier> DSRs.
> 
> Xavier> But Hugo's description in the same page said that
> Xavier> higher priority interrupts are enabled before calling
> Xavier> ISR. Which is true for nested interrupts?
> 
> Both are true, but depending on configuration. There is an option that
> allows nested interrupts - when disabled, the former is valid, when
> enabled, the latter is valid.
> 
> Xavier> If it's the former, should I rewrite the 'hal_cpu_int_enable'
> Xavier> macro used in hal_interrupt_stack_call_pending_DSRs (in
> Xavier> vector.S) to enable only higher priority interrupts? If it's
> 
> No. All interrupts are allowed when executing DSRs. DSRs are only
> executin when no interrupts are pending.

If there are some pending DSRs, it seems that these DSRs are executed 
in reverse order of interrupts/ISRs rather than in priority order. Does it
cause more unpredictability for a real-time system? Can DSRs be
prioritized? Is there a way to work around this?

Thanks.