Re: [ECOS] How to access PCI memory(HELP)....

[Nick Garnett <nickg at cygnus dot co dot uk>]

Jonathan Larmour <jlarmour@redhat.com> writes:

> Ling Su wrote:
> > 
> > > Jonathan Larmour wrote:
> > > >
> > > > >  BAR[0]    0x00410008 / probed size 0xFFFFF008 / CPU addr 0xC0410000
> > > >                                                             ^^^^^^^^^^
> > > >
> > > > Looks like this address is where the I/O ports for this card should have
> > >
> > > I mean "memory", not "I/O ports".
> > >
> > 
> > Thanks, Jifl.
> > 
> > You mean I can use 0xC0410000 pointer to access the PCI memeory, is that
> > correct? But what physical address will appear on the PCI bus then? I check
> > the source in platform.S for vrc4373, I didn't quite catch how the PCI
> > address and CPU address mapping for the window 0xC0xxxxxx, both the two PCI
> > memory access window registers are not configured for mapping this piece of
> > memory, you can refer the last message that I sent to you for more
> > information. I did  check the VR4373 manual, especially on the PCI interface
> > part, but I didn't quite get the idea how to transfter CPU 0xC0xxxxxx to PCI
> > address. Please do me a favor to give me some hints. Thanks!
> 
> After another look I now see what's going on. Yes, there is a problem here
> I believe and some of my understanding before was wrong(!) The relevant
> stuff is in hal_memc_setup_table (a table-driven initialization thing
> driven by hal_memc_setup) in platform.S.
> 
> In there, PCI_IOSPACE_BASE is set to 0x0c. This is used at the entry:
> 
> # Map PCI IO space Phys == Local
> .long   PCIMSTRIO,      (0x000fd000 | ( PCI_IOSPACE_BASE << 24) |
> PCI_IOSPACE_BASE)                                                                                              
> 
> So while the space is being mapped 1:1, it is indeed set up for 0x0C000000
> and not 0xC0000000, as you suggested.
> 
> The fix may be just changing the definition of 
> HAL_PCI_PHYSICAL_MEMORY_BASE in plf_io.h to 0x0C000000
> 
> Give that a go and let us know if it worked.
> 
> Nick, any comments?
> 

PCI_IOSPACE_BASE only maps PCI device IO registers, not memory
mappings. I don't believe we actually use any of these mappings, which
appear at 0x0C000000/0xAC000000 physical/logical addresses.

We also use the master address windows. Window one is set up to map
the 4372 control registers at 0x1C000000 in PCI space to
0x1C000000/0xBC000000 in the CPU. Window 2 maps 0x80000000 in PCI
space to 0x80000000 physical which the MMU remaps to 0xC0000000
logical. However, the 4372 also occupies the first 256Mb of this.

So, if my reading of the code and documentation is correct, then
HAL_PCI_PHYSICAL_MEMORY_BASE should be 0xD0000000, to skip the first
256Mb, and HAL_PCI_ALLOC_BASE_MEMORY should be 0x90000000. You should
then be able to access PCI device memory from 0xD0000000.

Of course currently the MMU only maps the first 256Mb of PCI space at
0xC0000000, so the MMU mapping needs to be extended. The simplest way
to do this is to increase NUMB_PG in platform.S from 8 to 16. The
current code appears to only use 16 of the 32 TLB entries, so using
all 32 will give 512Mb of mapped PCI memory.


Ling Su, please give this a try and if it works we can put these
values into the standard sources.


-- 
Nick Garnett, eCos Kernel Architect
Red Hat, Cambridge, UK