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RE: How to Enable FIQ while handling IRQs

Unless you're writing your own VSR for FIQ's, don't do this.  There is
much sensitive code in the IRQ VSR code just below these changes that
could fail if you got an FIQ while you were processing an IRQ.

My best suggestion would be to write your own FIQ VSR.  Note: FIQ means
"fast interrupt".  One probably does not want all the baggage of the
normal VSR/ISR/DSR handling for these sort of interrupts.

Look at .../ecc/hal/arm/edb7211/VVV/misc/ for examples of how this was
done on another ARM platform (this one from Cirrus Logic).  In this case,
I used FIQ to handle a high speed FIFO and could not afford any extra
instructions on the path.  If you totally replace the FIQ VSR then you
could avoid masking it in the code as you were thinking.

On 22-Jun-00 Amlan  Chakraborty wrote:
> Hi,
> I'm using ECOS for the ARM PID7T development board. My application
> requires that the FIQ interrupt vectors should
> never be disabled even when ecos is using IRQ routine for its scheduling
> and other work.
> 1. Can any one tell me if the IRQ isr used by ecos is re-entrant?
> 2. My understanding is that the FIQ is disabled at the start of IRQ VSR.
> Is this the only place where it is disabled ?
> 3. So Will removing the CPSR_FIQ_DISABLE bit from the cpsr programming
> in IRQ VSR of ecos keep the fiq enabled ?
> 4. If yes please confirm whether modifying vector.s as below will serve
> the purpose.
> ---code below from vector.s for ARM---
> IRQ:
>                              // Note: I use this exception stack while
> saving the context because
>                              // the current SP does not seem to be
> always valid in this CPU mode.
>                              ldr sp,.__exception_stack // get good stack
>                              sub lr,lr,#4  // PC at time of interrupt
>                              stmfd sp!,{r0,fp,ip,lr}
>                              mrs r0,spsr
>                              stmfd sp!,{r0}
>                              mov ip,sp   // save SP which will vanish
> with
>                                         //   mode switch
>                              mrs r0,cpsr   // switch to Supervisor Mode
>                              bic r0,r0,#CPSR_MODE_BITS
>                             //Original orr
>                              //modified below
>                              orr
> IRQ handler**/
> handle_IRQ_or_FIQ:
>                              msr cpsr,r0   // sp,lr are now old values
>                              mov fp,sp   // save old SP
> ...................................................
> Thanks in advance,
> Amlan

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