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Re: Example ISR,DSR for ARM AEB-1
- To: k e <ndgipper at yahoo dot com>
- Subject: Re: [ECOS] Example ISR,DSR for ARM AEB-1
- From: Jonathan Larmour <jlarmour at redhat dot co dot uk>
- Date: Wed, 09 Feb 2000 19:52:58 +0000
- CC: ecos-discuss at sourceware dot cygnus dot com
- Organization: Red Hat UK Ltd.
- References: <20000209185701.20301.qmail@web1103.mail.yahoo.com>
k e wrote:
>
> So, the creation of the ISR in the example you provide
> below will not interfere with the other ISRs?
> Maybe I'm confusing myself by reading the ARM chip
> sheets, but don't all external interrupts cause the
> same IRQ or FIQ to be activated? And, then it's up
> to the ISR to determine whether or not the external
> interrupt was from ext0 or ext1 or whatever? Maybe
> the OS is doing more than I thought it was.
Exactly so - when you talk about ISRs in eCos, you are talking about
interrupt handlers where the source of the interrupt has already been
determined (from the interrupt controller). If you wanted direct control of
the IRQ processor interrupt itself (which is what you were thinking about)
we would call that attaching a VSR (Vectored Service Routine) in eCos, and
in that case you would indeed get all external interrupts no matter what the
source.
On the AEB, the decoding is done in hal/aeb/VERSION/src/aeb_misc.c, for
example here's what it is in my code right now for that:
//
// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
// Do hardware-level IRQ handling
int irq_status, vector;
HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status);
for (vector = 0; vector < 16; vector++) {
if (irq_status & (1<<vector)) return vector;
}
return CYGNUM_HAL_INTERRUPT_unused; // This shouldn't happen!
}
Hope this helps,
Jifl
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