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[Bug 1001468] eCos GNU tools 4.6.2


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--- Comment #40 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-18 13:06:07 GMT ---
(In reply to comment #39)
> Created an attachment (id=1648)
 --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1648) [details]
> Prospective GDB patch (against GDB trunk) for Cortex-M4F registers (fixed)
> 
> Revised version of the patch I just attached - I made a silly omission. Ignore
> the previous.

Thank you Jifl.

I'll try this. However, please note that despite having double registers
d0..d15 Cortex-M4F has hardware support only for single precision FP arithmetic
so single precision view of registers (s0..s31 instead of d0..d15) would be
more useful for floating point representation of register contents. Double
precision floating point is actually done in software and does not involve
d0..d15, at least not with GCC. Single precision naturally uses s0..s31 VFP
registers. Below there is a code sample.

void main(void)
{
    volatile float fla, flb, flc;
    volatile double dla, dlb, dlc;

    printf("Enter floats: ");
    scanf("%f %f", &fla, &flb);
    printf("Enter doubles: ");
    scanf ("%lf %lf", &dla, &dlb);

    flc = fla + flb;

    dlc = dla + dlb;

    printf("%f + %f = %f\n", fla, flb, flc);
    printf("%f + %f = %f\n", dla, dlb, dlc);
}

Disassembly gives:

    flc = fla + flb;
1fff0536:    ed9d 7a0b     vldr    s14, [sp, #44]    ; 0x2c
1fff053a:    eddd 7a0c     vldr    s15, [sp, #48]    ; 0x30
1fff053e:    ee77 7a27     vadd.f32    s15, s14, s15

    dlc = dla + dlb;
1fff054a:    e9dd 0104     ldrd    r0, r1, [sp, #16]
1fff054e:    e9dd 2306     ldrd    r2, r3, [sp, #24]
1fff0552:    f007 fa3b     bl    1fff79cc <__adddf3>
1fff0556:    e9cd 0108     strd    r0, r1, [sp, #32]

Ilija

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