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[Bug 1001434] New: can_lpc2xxx_baudrates.h has some erroneous bittiming entries
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: unassigned at bugs dot ecos dot sourceware dot org
- Date: Tue, 27 Dec 2011 19:45:13 +0000
- Subject: [Bug 1001434] New: can_lpc2xxx_baudrates.h has some erroneous bittiming entries
- Auto-submitted: auto-generated
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Summary: can_lpc2xxx_baudrates.h has some erroneous bit timing
entries
Product: eCos
Version: CVS
Platform: Other (please specify)
OS/Version: Cortex-M
Status: UNCONFIRMED
Severity: normal
Priority: low
Component: CAN
AssignedTo: unassigned@bugs.ecos.sourceware.org
ReportedBy: bernard.fouche@kuantic.com
CC: ecos-bugs@ecos.sourceware.org
Class: Advice Request
Hello.
I've started to port the LPC2XXX CAN driver to the LPC17XX
variant. I'm checking the bit rate calculations and it is obvious that
the 30MHz values were done with a copy/paste of the 60MHz values, so I
rechecked everything.
It appears that some of the existing entries have wrong values for
some bit rate and some entries are described as 'not supported' while
they can be supported. IMHO, an entry should be marked 'not supported'
instead of having non-zero values (800Kb/s with a 30MHz clock).
Here is a copy of the part of the file showing the errors. I've
detailed each calculation check in comments and I propose to keep
these comments detailing the calculation: if someone wants to check
the calculations it is easier to understand, and if someone wants to
add another clock speed it's easier to have all the examples at hand.
Since I need 8Mhz and 16Mhz clocking, I've added the corresponding
entries. If this bug is confirmed, I propose to post a corrected file
for all clocks using the comments shown for 8Mhz & 16MHz.
It's possible that the future corrected file will also allow one to
declare its own bit rate definition from the CDL since sometimes there
are CAN buses that have strict usage rules (for instance it's
forbidden to perform triple sampling at 250Kbp/s in ISO-15765-4 (don't
ask me why!) while all the following definitions set it up to
250Kbp/s).
<nitpick>In a perfect world, 'baud' have to be replaced in the
comments by 'bit/s' since CAN sometimes use more than one bit to
represent a CAN 'symbol' and what is set here is the bit
time</nitpick>
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 60000000
//
// Table with register values for baudrates at peripheral clock of 60 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// Should be (299,15,2,0,1), BRP+1 has been forgotten
// 60MHz/(299+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
CAN_BR_TBL_ENTRY(300, 15, 2, 0, 1), // 10 kbaud
// Should be (149,15,2,0,1), BRP+1 has been forgotten
// 60MHz/(149+1)=400KHz, 400KHz/(15+2+3)=20Kb/s
CAN_BR_TBL_ENTRY(150, 15, 2, 0, 1), // 20 kbaud
// 60MHz/(59+1)=1MHz, 1MHz/(15+2+3)=50Kb/s
CAN_BR_TBL_ENTRY(59, 15, 2, 0, 1), // 50 kbaud
// 60MHz/(39+1)=1.5MHz, 1.5MHz/(11+1+3)=100Kb/s
CAN_BR_TBL_ENTRY(39, 11, 1, 0, 1), // 100 kbaud
// 60MHz/(29+1)=2MHz, 2MHz/(12+1+3)=125Kb/s
CAN_BR_TBL_ENTRY(29, 12, 1, 0, 1), // 125 kbaud
// 60MHz/(14+1)=4MHz, 4MHz/(12+1+3)=250Kb/s
CAN_BR_TBL_ENTRY(14, 12, 1, 0, 1), // 250 kbaud
// 60MHz/(7+1)=7.5MHz, 7.5MHz/(11+1+3)=500Kb/s
CAN_BR_TBL_ENTRY( 7, 11, 1, 0, 0), // 500 kbaud
// 60MHz/(4+1)=12MHz, 12MHz/(11+1+3)=800Kb/s
CAN_BR_TBL_ENTRY( 4, 11, 1, 0, 0), // 800 kbaud
// 60MHz/(3+1)=15MHz, 15MHz/(11+1+3)=1Mb
CAN_BR_TBL_ENTRY( 3, 11, 1, 0, 0), // 1000 kbaud
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 60000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 30000000
//
// Table with register values for baudrates at peripheral clock of 30 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// Why 'not supported'? We can get similar values with 60MHz clocking:
// 30MHz/(149+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
// -> (149,15,2,0,1)
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // 10 kbaud - not supported
// Why 'not supported'? We can get similar values with 60MHz clocking:
// 30MHz/(74+1)=400KHz, 400KHz/(15+2+3)=20Kb/s
// -> (74,15,2,0,1)
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // 20 kbaud - not supported
// Should be (29,11,1,9,1): 30MHz/(29+1)=1MHz, 1MHz/(15+2+3)=50Kb/s
CAN_BR_TBL_ENTRY(59, 15, 2, 0, 1), // 50 kbaud
// Should be (14,15,2,0,1): 30MHz/(14+1)=2MHz, 2MHz/(15+2+3)=100Kb/s
CAN_BR_TBL_ENTRY(39, 11, 1, 0, 1), // 100 kbaud
// Should be (15,11,1,0,1): 30MHz/(15+1)=1.875MHz, 1.875MHz/(11+1+3)=125Kb/s
CAN_BR_TBL_ENTRY(29, 12, 1, 0, 1), // 125 kbaud
// Should be (7,11,1,0,1): 30MHz/(7+1)=3.750MHz, 3.750MHz/(11+1+3)=250Kb/s
CAN_BR_TBL_ENTRY(14, 12, 1, 0, 1), // 250 kbaud
// Should be (3,11,1,0,0): 30MHz/(3+1)=7.5MHz,7.5MHz/(11+1+3)=500Kb/s
CAN_BR_TBL_ENTRY( 7, 11, 1, 0, 0), // 500 kbaud
// Wrong! 30MHz/(4+1)=6MHz, 6MHz/(11+1+3)=400Kb/s, not 800Kbps!
// Can't find a way to get 800Kb/s with 30MHz clock: @60MHz, it is
// possible to divide the clock by 5 (4+1), however with 30MHz, one can't
// divide the clock by 2.5. Keeping the divide by 5, then we can't divide
// 6MHz by 7.5...
// I vote for 'not supported' if all entries must have exactly
// the required bit rate.
CAN_BR_TBL_ENTRY( 4, 11, 1, 0, 0), // 800 kbaud
// Should be (1,11,1,0,0): 30MHz/(1+1)=15MHz,15MHz/(11+1+3)=1Mb
CAN_BR_TBL_ENTRY( 3, 11, 1, 0, 0), // 1000 kbaud.
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 30000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 15000000
//
// Table with register values for baudrates at peripheral clock of 15 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// 15MHz/(59+1)=250KHz, 250KHz/(15+7+3)=10Kb/s
CAN_BR_TBL_ENTRY(59, 15, 7, 0, 1), // 10 kbaud
// 15MHz/(49+1)=3MHz, 3MHz/(11+1+3)=20Kb/s
CAN_BR_TBL_ENTRY(49, 11, 1, 0, 1), // 20 kbaud
// 15MHz/(19+1)=750KHz, 750KHz/(11+1+3)=50Kb/s
CAN_BR_TBL_ENTRY(19, 11, 1, 0, 1), // 50 kbaud
// 15MHz/(9+1)=1.5MHz, 1.5MHz/(11+1+3)=100Kb/s
CAN_BR_TBL_ENTRY( 9, 11, 1, 0, 1), // 100 kbaud
// 15MHz/(7+1)=1.875MHz, 1.875MHz/(11+1+3)=125Kb/s
CAN_BR_TBL_ENTRY( 7, 11, 1, 0, 1), // 125 kbaud
// 15MHz/(3+1)=3.750MHz, 3.750MHz/(11+1+3)=250Kb/s
CAN_BR_TBL_ENTRY( 3, 11, 1, 0, 1), // 250 kbaud
// 15MHz/(1+1)=7.5MHz, 7.5MHz/(11+1+3)=500Kb/s
CAN_BR_TBL_ENTRY( 1, 11, 1, 0, 0), // 500 kbaud
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // 800 kbaud - not supported
// 15MHz/(0+1)=15MHz, 15MHz/(11+1+3)=1Mb
CAN_BR_TBL_ENTRY( 0, 11, 1, 0, 0), // 1000 kbaud
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 15000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 48000000
//
// Table with register values for baudrates at peripheral clock of 48 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// Why 'not supported'?
// 48MHz/(239+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
// -> (239,15,2,0,1) seems fine
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // 10 kbaud - not supported
// Why 'not supported'?
// 48MHz/(119+1)=400KHz, 400KHz/(15+2+3)=20Kb/s
// -> (119,15,2,0,1) seems fine
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // 20 kbaud - not supported
// 48MHz/(59+1)=800KHz, 800KHz/(12+1+3)=50Kb/s
CAN_BR_TBL_ENTRY(59, 12, 1, 0, 1), // 50 kbaud
// 48MHz/(29+1)=1.6MHz, 1.6MHz/(12+1+3)=100Kb/s
CAN_BR_TBL_ENTRY(29, 12, 1, 0, 1), // 100 kbaud
// 48MHz/(23+1)=2MHz, 2MHz/(12+1+3)=125Kb/s
CAN_BR_TBL_ENTRY(23, 12, 1, 0, 1), // 125 kbaud
// 48MHz/(11+1)=4MHz, 4MHz/(12+1+3)=250Kb/s
CAN_BR_TBL_ENTRY(11, 12, 1, 0, 1), // 250 kbaud
// 48MHz/(5+1)=8MHz, 8MHz/(12+1+3)=500Kb/s
CAN_BR_TBL_ENTRY( 5, 12, 1, 0, 0), // 500 kbaud
// 48MHz(3+1)=12MHz, 12MHz/(11+1+3)=800Kb/s
CAN_BR_TBL_ENTRY( 3, 11, 1, 0, 0), // 800 kbaud
// 48MHz(2+1)=16MHz, 16MHz/(12+1+3)=1Mb
CAN_BR_TBL_ENTRY( 2, 12, 1, 0, 0), // 1000 kbaud
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 48000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 24000000
//
// Table with register values for baudrates at peripheral clock of 24 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// Why 'not supported'?
// 24MHz/(119+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
// ->(119,15,2,0,1)
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // 10 kbaud - not supported
// 24MHz/(59+1)=400KHz, 400KHz/(15+2+3)=20Kb/s
CAN_BR_TBL_ENTRY(59, 15, 2, 0, 1), // 20 kbaud
// 24MHz/(29+1)=800KHz, 800KHz/(12+1+3)=50Kb/s
CAN_BR_TBL_ENTRY(29, 12, 1, 0, 1), // 50 kbaud
// 24MHz/(14+1)=1.6MHz, 1.6MHz/(12+1+3)=100Kb/s
CAN_BR_TBL_ENTRY(14, 12, 1, 0, 1), // 100 kbaud
// 24MHz/(11+1)=2MHz, 2MHz/(12+1+3)=125Kb/s
CAN_BR_TBL_ENTRY(11, 12, 1, 0, 1), // 125 kbaud
// 24MHz/(5+1)=4MHz, 4MHz/(12+1+3)=250Kb/s
CAN_BR_TBL_ENTRY( 5, 12, 1, 0, 1), // 250 kbaud
// 24MHz/(2+1)=8MHz, 8MHz/(12+1+3)=500Kp/s
CAN_BR_TBL_ENTRY( 2, 12, 1, 0, 0), // 500 kbaud
// 24MHz/(1+1)=12MHz, 12MHz/(11+1+3)=800Kb/s
CAN_BR_TBL_ENTRY( 1, 11, 1, 0, 0), // 800 kbaud
// Wrong!
// 24MHz/(1+1)=12MHz, 12MHz/(5+0+3)=1.5Mb/s!
// To have 1M/s we need a 12 or 24 Tq bit time:
// 24MHz/(0+1)=24MHz, 24MHz/(17+4+3)=1Mb/s or, for instance,
// -> (0,17,4,0,0)
// 24MHz/(1+1)=12MHz, 12MHz/(7+2+3)=1Mb/s
// -> (1,7,2,0,0)
// (other tseg1/tseg2 values are possible)
// PROBLEM: who knows reasonnable TSEG1/TSEG2 balance for 1Mb/s?
CAN_BR_TBL_ENTRY( 1, 5, 0, 0, 0), // 1000 kbaud
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 24000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 16000000
//
// Table with register values for baudrates at peripheral clock of 16 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// 16MHz/(79+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
CAN_BR_TBL_ENTRY(79, 15, 2, 0, 1), // 10 Kb/s
// 16MHz/(39+1)=400KHz, 400KHz/(15+2+3)=20Kb/s
CAN_BR_TBL_ENTRY(39, 15, 2, 0, 1), // 20 Kb/s
// 16MHz/(19+1)=800KHz, 800KHz/(12+1+3)=50Kb/s
CAN_BR_TBL_ENTRY(19, 12, 1, 0, 1), // 50 Kb/s
// 16MHz/(7+1)=2MHz, 2MHz/(15+2+3)=100Kb/s
CAN_BR_TBL_ENTRY( 7, 15, 2, 0, 1), // 100 Kb/s
// 16MHz/(7+1)=2MHz, 2MHz/(12+1+3)=125Kb/s
CAN_BR_TBL_ENTRY( 7, 12, 1, 0, 1), // 125 Kb/s
// 16MHz/(3+1)=4MHz, 4MHz/(12+1+3)=250Kb/s
CAN_BR_TBL_ENTRY( 3, 12, 1, 0, 1), // 250 Kb/s
// 16MHz/(1+1)=8MHz, 8MHz/(12+1+3)=500Kb/s
CAN_BR_TBL_ENTRY( 1, 12, 1, 0, 0), // 500 Kb/s
// 16MHz/(0+1)=16MHz, 16MHz/(15+2+3)=800Kb/s
CAN_BR_TBL_ENTRY( 0, 15, 2, 0, 0), // 800 Kb/s
// 16MHz/(0+1)=16MHz, 16MHz/(12+1+3)=1Mb/s
CAN_BR_TBL_ENTRY( 0, 12, 1, 0, 0), // 1000 Kb/s
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 16000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 12000000
//
// Table with register values for baudrates at peripheral clock of 12 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// Comment error: is supported!
// 12MHz/(59+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
CAN_BR_TBL_ENTRY(59, 15, 2, 0, 1), // 10 kbaud - not supported
// 12MHz/(39+1)=300KHz, 300KHz/(11+1+3)=20Kb/s
CAN_BR_TBL_ENTRY(39, 11, 1, 0, 1), // 20 kbaud
// 12MHz/(14+1)=800KHz, 800KHz/(12+1+3)=50Kb/s
CAN_BR_TBL_ENTRY(14, 12, 1, 0, 1), // 50 kbaud
// 12MHz/(7+1)=1.5MHz, 1.5MHz/(11+1+3)=100Kb/s
CAN_BR_TBL_ENTRY( 7, 11, 1, 0, 1), // 100 kbaud
// 12MHz/(5+1)=2MHz, 2MHz/(12+1+3)=125Kb/s
CAN_BR_TBL_ENTRY( 5, 12, 1, 0, 1), // 125 kbaud
// 12MHz/(2+1)=4MHz, 4MHz/(12+1+3)=250Kb/s
CAN_BR_TBL_ENTRY( 2, 12, 1, 0, 1), // 250 kbaud
// 12MHz/(2+1)=4MHz, 4MHz/(5+0+3)=500Kb/s
// Should remove the '0' before '5'...
CAN_BR_TBL_ENTRY( 2, 05, 0, 0, 0), // 500 kbaud
// 12MHz/(0+1)=12MHz, 12MHz/(11+1+3)=800Kb/s
CAN_BR_TBL_ENTRY( 0, 11, 1, 0, 0), // 800 kbaud
// 12MHz/(0+1)=12MHz, 12MHz/(9+O+3)=1Mb/s
CAN_BR_TBL_ENTRY( 0, 9, 0, 0, 0), // 1000 kbaud
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 12000000
#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 8000000
//
// Table with register values for baudrates at peripheral clock of 8 MHz
//
static const cyg_uint32 lpc2xxx_br_tbl[] =
{
// 8MHz/(39+1)=200KHz, 200KHz/(15+2+3)=10Kb/s
CAN_BR_TBL_ENTRY(39, 15, 2, 0, 1), // 10 Kb/s
// 8MHz/(19+1)=400KHz, 400KHz/(15+2+3)=20Kb/s
CAN_BR_TBL_ENTRY(19, 15, 2, 0, 1), // 20 Kb/s
// 8MHz/(7+1)=800KHz, 800KHz/(12+1+3)=50Kb/s
CAN_BR_TBL_ENTRY(7, 12, 1, 0, 1), // 50 Kb/s
// 8MHz/(7+1)=1.5MHz, 1.5MHz/(11+1+3)=100Kb/s
CAN_BR_TBL_ENTRY( 7, 11, 1, 0, 1), // 100 Kb/s
// 8MHz/(3+1)=2MHz, 2MHz/(12+1+3)=125Kb/s
CAN_BR_TBL_ENTRY( 3, 12, 1, 0, 1), // 125 Kb/s
// 8MHz/(1+1)=4MHz, 4MHz/(12+1+3)=250Kb/s
CAN_BR_TBL_ENTRY( 1, 12, 1, 0, 1), // 250 Kb/s
// 8MHz/(0+1)=8MHz, 8MHz/(12+1+3)=500Kb/s
CAN_BR_TBL_ENTRY( 0, 12, 1, 0, 0), // 500 Kb/s
// 8MHz/(0+1)=8MHz, 8MHz/(6+1+3)=800Kb/s
CAN_BR_TBL_ENTRY( 0, 6, 1, 0, 0), // 800 Kb/s
// 8MHz/(0+1)=8MHz, 8MHz/(5+O+3)=1Mb/s
CAN_BR_TBL_ENTRY( 0, 9, 0, 0, 0), // 1000 Kb/s
CAN_BR_TBL_ENTRY( 0, 0, 0, 0, 0), // Autobaud - not supported
};
#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 8000000
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