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[Bug1001300] problÃme de commutation des taches
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: unassigned at bugs dot ecos dot sourceware dot org
- Date: Fri, 5 Aug 2011 13:06:49 +0100
- Subject: [Bug1001300] problÃme de commutation des taches
- Auto-submitted: auto-generated
- References: <bug-1001300-777@http.bugs.ecos.sourceware.org/>
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--- Comment #5 from atef <benhajatef@yahoo.fr> 2011-08-05 13:06:45 BST ---
(In reply to comment #4)
> First of all IÂwant toÂthankÂyou for your help.ÂHere isÂa description of the
> architecture thatÂIÂused andÂdebugger.
> GdbServer tool is a software debugger for SocLib. It listens for TCP
> connection from Gnu GDB clients :GNU gdb 7.0
> platform mips32_soclib contains:
> *processor mips32 : It implements all instructions defined in the MIPS32
> architecture specification, with the following limitations:
> The floating point instructions are supported, FPU exception detection is
> partially implemented
> The Mips virtual memory instructions are not supported. The MMU is implemented
> as an external TLB (SoCLib generic).
> Both little-endian and big-endian implementations are available.
> Mips defines 6 interrupts lines. The handling and prioritization of the
> interrupts is deferred to software
> *VciXicu: memory mapped Hardware interrupt + Timer + IPI controller
> *Segment of Ram
(In reply to comment #4)
> First of all IÂwant toÂthankÂyou for your help.ÂHere isÂa description of the
> architecture thatÂIÂused andÂdebugger.
> GdbServer tool is a software debugger for SocLib. It listens for TCP
> connection from Gnu GDB clients :GNU gdb 7.0
> platform mips32_soclib contains:
> *processor mips32 : It implements all instructions defined in the MIPS32
> architecture specification, with the following limitations:
> The floating point instructions are supported, FPU exception detection is
> partially implemented
> The Mips virtual memory instructions are not supported. The MMU is implemented
> as an external TLB (SoCLib generic).
> Both little-endian and big-endian implementations are available.
> Mips defines 6 interrupts lines. The handling and prioritization of the
> interrupts is deferred to software
> *VciXicu: memory mapped Hardware interrupt + Timer + IPI controller
> *Segment of Ram
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