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Re: Help needed regarding 'tlbre' instruction.


All,

Please find attached the file (part of the
file).Attached are the only addition made to the
arch/ppc/boot/simple/head.S file to support DUART
related initialization in MPC85xx (STx GP3 board). 

As I mentioned in earlier mail, I am having trouble
using 'tlbre','msync' instructions. I tried to fix
this by adding "-mbooke"/"-me500" flag to
simple/Makefile. The problem with tlbre, msync .. goes
away but I get the foll error message:

>>
  AS      arch/ppc/boot/simple/head.o
  AS      arch/ppc/boot/simple/relocate.o
arch/ppc/boot/simple/relocate.S: Assembler messages:
arch/ppc/boot/simple/relocate.S:150: Error:
Unrecognized opcode: `iccci'
arch/ppc/boot/simple/relocate.S:150: Error:
Unrecognized opcode: `dccci'
...
make[2]: *** [arch/ppc/boot/simple/relocate.o] Error 1
make[1]: *** [simple] Error 2
make: *** [zImage] Error 2
<<

Brief background on why this change was made:
When we boot the board using the zImage.stx (I am
using a customized linux kernel, not uImage), nothing
comes up on the console. Figured out that the code is
trying to use e0000000 for DUART. But, also saw that
uBoot uses ff700000 for UART initially, later maps TLB
entries for ff700000 to e0000000 and then start using
e0000000 DUART base. 

Can somebody help in this regard?

Thanks,
Vinay.

--- Khem Raj <khem@mvista.com> wrote:

> vinay hegde said the following on 07/26/2006 04:49
> AM:
> > Hi,
> >
> > I am trying to compile the 8555 BSP (BookE
> > architecture) with Linux kernel 2.6.13.4. I have
> > modified some files (head.S for example) with some
> > part of u-Boot code for specific req. But, it
> seems
> > that 'tlbre' instruction is not supported in my
> > environment. 
> >   
> post what change you made.
> 
> --
> For unsubscribe information see
> http://sourceware.org/lists.html#faq
> 
> 



		
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{\rtf1\ansi\ansicpg1252\deff0\deflang1033{\fonttbl{\f0\fmodern\fprq1\fcharset0 Courier New;}} {\*\generator Msftedit 5.41.15.1507;}\viewkind4\uc1\pard\f0\fs20 /* Note:\par #define CFG_CCSRBAR_DEFAULT 0xff700000\par #define CFG_CCSRBAR 0xe0000000\par */\par \par /* arch/ppc/boot/simple/head.S */\par ...\par ...\par #if defined(CONFIG_8xx) || defined(CONFIG_85xx)\par mfmsr r8 /* Turn off interrupts */\par li r9,0\par ori r9,r9,MSR_EE\par andc r8,r8,r9\par mtmsr r8\par \par /* We do this because some boot roms don't initialize the\par * processor correctly. Don't do this if you want to debug\par * using a BDM device.\par */\par li r4,0 /* Zero DER to prevent FRZ */\par mtspr SPRN_DER,r4\par #endif\par \par #if defined(CONFIG_85xx)\par \par /* storing the registers for future use */\par mr r11,r3\par mr r12,r4\par mr r13,r5\par mr r14,r6\par \par /*\par * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then\par * write it back immediately to fixup a Rev 1 bug (Errata CPU4)\par * for this initial TLB1 entry 0, otherwise the TLB1 entry 0\par * will be invalidated (incorrectly).\par */\par lis r2,0x1000\par mtspr MPC85xx_MAS0,r2 /* renaming MAS0 to MPC85xx_MAS0 to avoid conflict -- vinay */\par tlbre\par tlbwe\par isync\par \par /*\par * Invalidate all TLB0 entries.\par */\par li r3,4\par li r4,0\par tlbivax r4,r3\par \par /*\par * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.\par * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB\par * region before we can access any CCSR registers such as L2\par * registers, Local Access Registers,etc. We will also re-allocate\par * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.\par *\par * Please refer to board-specif directory for TLB1 entry configuration.\par * (e.g. board/<yourboard>/init.S)\par *\par */\par \par /* bl tlb1_entry -- replacing the tlb1_entry inline - vinay*/\par \par /* Some problem while using TLB1_MAS0/1/2/3 (...) macros, so calculated the macros \par return values manually and moving them to MAS0/1/2/3. temporary hack -- vinay */\par \par /* This one's for CFG_CCSRBAR_DEFAULT -- vinay */\par \tab mtspr MPC85xx_MAS0,0 \par \par \tab lis r16,0x8000\par ori r16,r16,0x0000\par mtspr MPC85xx_MAS1,r16\par \par \tab lis r16,0xff70\par ori r16,r16,0x000a\par mtspr MPC85xx_MAS2,r16\par \par \tab lis r16,0xff70\par ori r16,r16,0x0015\par mtspr MPC85xx_MAS3,r16\par \par \tab isync\par msync\par tlbwe\par isync\par \par /* This one's for CFG_CCSRBAR -- vinay */\par \tab lis r16,0x1005\par ori r16,r16,0x0000\par mtspr MPC85xx_MAS0,r16\par \par lis r16,0xc000\par ori r16,r16,0x0800\par mtspr MPC85xx_MAS1,r16\par \par lis r16,0xe000\par ori r16,r16,0x000a\par mtspr MPC85xx_MAS2,r16\par \par lis r16,0xe000\par ori r16,r16,0x0015\par mtspr MPC85xx_MAS3,r16\par \par isync\par msync\par tlbwe\par isync\par \par #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)\par /* Special sequence needed to update CCSRBAR itself */\par lis r4, CFG_CCSRBAR_DEFAULT@h\par ori r4, r4, CFG_CCSRBAR_DEFAULT@l\par \par lis r5, CFG_CCSRBAR@h\par ori r5, r5, CFG_CCSRBAR@l\par srwi r6,r5,12\par stw r6, 0(r4)\par isync\par \par lis r5, 0xffff\par ori r5,r5,0xf000\par lwz r5, 0(r5)\par isync\par \par lis r3, CFG_CCSRBAR@h\par lwz r5, CFG_CCSRBAR@l(r3)\par isync\par #endif\par \par /* Restoring the original registers back .. */\par mr r3,r11\par mr r4,r12\par mr r5,r13\par mr r6,r14\par \par #endif /* CONFIG_85xx */\par \par \par #if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP)\par mr r4,r29 /* put the board info pointer where the relocate\par * routine will find it\par */\par #endif\par \par /* Get the load address.\par */\par subi r3, r3, 4 /* Get the actual IP, not NIP */\par b relocate\par }
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