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Rich, Thanks for your reply. My understanding of the nop instruction is that when it is executed it synchronises the instruction pipeline by waiting for previous instructions to complete before continuing. I think this would tend to slow execution rather than speeding it up. However in this case, the nop is never executed because it is after the rts. It gets pre-fetched and then flushed. I have confirmed that the execution speed is the same on my target (a CPU32) with or without it. Maybe it has some effect on other members of the family. Regards, Chris > -----Original Message----- > From: Rich Pinkall-Pollei [SMTP:whraven@msn.fullfeed.com] > Sent: Thursday, January 13, 2000 3:41 PM > To: crossgcc@sourceware.cygnus.com > Cc: Palmer.Chris > Subject: Re: m68k-coff-gcc and NOPs > > +-+-----------------------------------------------------------------+-+ > |o| |o| > |o| > Does anybody know why the 68K version of gcc compiles a |o| > |o| > NOP instruction at the end of each function, after the |o| > |o| > RTS? |o| > |o| |o| > +-+-----------------------------------------------------------------+-+ > > It's been a long time since I worked with the Motorola chips, but if I > remember correctly, the design of the instruction pipeline required a > NOP after the return instruction for best performance. > > > > > > ------ > Want more information? See the CrossGCC FAQ, > http://www.objsw.com/CrossGCC/ > Want to unsubscribe? Send a note to > crossgcc-unsubscribe@sourceware.cygnus.com ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sourceware.cygnus.com
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