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Re: Hitachi SH-2 UBC help needed

Bill Gatliff wrote 

Has anyone used the Hitachi SH-2 microprocessor's User Break Controller
I have used it for some debugging, it is the only way to set a
breakpoint when I execute from Flash
All the examples in the SH-2 manual show the case where you know the
address of an instruction a-priori, and you then set that address in the
UBAR registers.  If I stick with this approach, then I'm forced to do a
bit of disassembly at runtime to determine where the instruction about
to be executed will go, so that I can generate a UBC exception after it
No dissasembly is needed, if you know the address at which you start
execution, just add 2 since all instructions are 16 bits long. Since all
branch instructions have a delay slot, the next instruction is always
fetched. If you set the break on the delay slot instruction the break
happens after the instruction so the PC is still good. The only
instruction that you may have to check for is the TRAP n, in which case
you will only break when you do the RTE.
What I would prefer to do is simply disable interrupts, configure the
UBC to generate an exception on *any* fetch (UBAMRH/L == 0xffff), and
then do an RTE.  What I'm hoping is that the instruction waiting after
the RTE will finish before the UBC exception is taken...
Is this feasible?  The japlish documentation isn't really clear on this
point, but it would seem to be a real oversight on Hitachi's part if
this wouldn't work...
Never tried this, it could work if the interrupt mask was high enough
(15) since although the UBR would generate the interrupt immediately on
setting the UBR registers, the Interrupt Controller would only generate
the TRAP after executing the RTE.
Stan Katz

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