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Re: Atomic Operations (continuing on from Masking Interrupts?)
On Tue, Jul 06, 1999 at 10:40:48AM -0700, David Querbach wrote:
> In our system, we have a target-dependent header file that defines four
> - enableInts() unconditionally enables interrupts
> - disableInts() unconditionally disables interrupts
> - inhibitInts() saves the CPU's interrupt mask bit in an auto variable,
> then invokes disableInts()
> - restoreInts() sets the CPU's interrupt mask bit from the auto variable
> written by inhibitInts().
Right - I use these, too (however, in my case, inhibitInts returns the old
mask value, which restoreInts writes back to the SR). However, the problem
is that these disable *all* interrupts, and increase latencies. In many
cases, all I need is a single atomic instruction.
I can either write this in assembler, or use C with inline assembler. Gcc
tends to produce code that is 'quite good' compared to assembler, and the
code is a lot easier to maintain - however I don't want to waste extra
cycles in short interrupt handlers.
I realize that both are not portable, but when I write code for a special
target, portability may not be as important as efficiency.
Michael Schwingen, Ahornstrasse 36, 52074 Aachen
New CrossGCC FAQ: http://www.objsw.com/CrossGCC
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