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Re: unable to find precise mode to match cpu word-bitsize 24
- From: Dave Korn <dave dot korn dot cygwin at googlemail dot com>
- To: Doug Evans <dje at sebabeach dot org>
- Cc: Dave Korn <dave dot korn dot cygwin at googlemail dot com>, cgen at sources dot redhat dot com
- Date: Sun, 05 Jul 2009 00:47:31 +0100
- Subject: Re: unable to find precise mode to match cpu word-bitsize 24
- References: <4A3E86AA.2080002@gmail.com> <4A3EBD0E.5080109@sebabeach.org> <4A3ECDBB.1000806@gmail.com> <4A3FB9D5.9070103@sebabeach.org>
Doug Evans wrote:
> Dave Korn wrote:
>> Doug Evans wrote:
>>
>>
>>> This is new ground so we can decide how we want things to look, and then
>>> make it work.
>>>
>>
>> Well, what I'd particularly like in this case would be for my pc to
>> increment by one for each 24-bit insn, rather than have the model
>> pretend to
>> be an 8-bit CISC machine processing all 3-byte instructions, if you
>> see what I
>> mean.
>>
>
> Righto. That should be doable regardless.
I hope so. Should I just take the blunt sledgehammer approach, and define
setters and getters for hardware units h-addr and h-iaddr that multiply/divide
by 3 on the fly, and let the underlying framework pretend it's a CISC machine
that uses 3-byte operands and data? Or is there a cleaner way to go?
cheers,
DaveK