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Re: copyright issues for cgen-generated tools
Hi -
On Tue, Jan 16, 2007 at 01:28:56PM +0000, Joern Rennecke wrote:
> [...]
> The features I hoped to re-use from the sh port cpu are variable length
> instruction parsing for a bi-endian cpu that is actually (insn-lsb0? #t),
> and delay slot handling for the simulators. [...]
Go ahead.
> Also, worrying about m32r.cpu is that it has ChangeLog entries that
> are newer than the Copyright notices. [...]
I'm sure that's just sloppy copyright date updating.
> [...]
> I'm thinking of using something like the code below; does that make sense?
> [...]
> (dnmf f-rel21 "21 bit pc relative signed offset" (PCREL-ADDR) INT
> (f-d21l f-d21h)
> (sequence () ; insert
> (set (ifield f-d21l)
> (and (srl (sub (ifield f-rel21) (and pc (const -4)))
> (const 1))
> (const #x3ff)))
> (set (ifield f-d21h)
> (sra (sub (ifield f-rel21) (and pc (const -4)))
> (const 11)))
> )
> [...]
Yes, if the "current pc" were thusly available. I believe however
that it is not, and that this will likely require hand-crafted
assembler operand parsers / relocations, and all that good stuff.
For an older Cygnus-authored target port, we built something called
"complex relocations", which can be used to automatically encode
complex link-time expressions into assembly operands. IIRC this part
is being prepared for contribution to the FSF code base, but this is
bound to be a controversial addition.
- FChE