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Re: [RFA:] Fix breakage of manually building SID CPU

Hi -

> But it's not.  A delayed branch doesn't (necessarily or usually)
> run in parallel with the delayed instruction or the one after
> the delayed one.

One could sort of consider the delayed update to PC running in
parallel with the next instruction, sort of.  I don't recall all
aspects of the design/notational decisions now.  The work was
certainly done for a processor that was "worst" of all worlds in terms
of VLIW and open pipelines.  Association with the cpu "parallel" field
may have been for simplicity, using that as a mode selector instead of
searching through the entire rtl for occurrences of (delay).

See also: http://sourceware.org/ml/cgen/2003-q1/msg00004.html

- FChE
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