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[patch][rfa]@arch@_cgen_ifld_table
- From: Dave Brolley <brolley at redhat dot com>
- To: cgen at sources dot redhat dot com
- Date: Tue, 11 Feb 2003 15:19:29 -0500
- Subject: [patch][rfa]@arch@_cgen_ifld_table
- Organization: Red Hat Canada, Ltd
Hi,
Stan Cox noticed the following when debugging a problem with one of our
internal ports. I've replaced the name of the port with '@arch@' and
'@ARCH@' below:
-------------------------------------------------------------------------
I notice that @arch@-opc.c defines:
#define F(f) & @arch@_cgen_ifld_table[@ARCH@_ ##f]
so it would seem as though the members of @arch@_cgen_ifld_table should
match those of enum ifield_type. However they do not always do so;
they seem to get out of sync for multi-ifields.
(@arch@-desc.c)
{ @ARCH@_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ @ARCH@_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ @ARCH@_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ @ARCH@_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
versus (@arch@-desc.h)
, @ARCH@_F_CSRN_HI, @ARCH@_F_CSRN_LO, @ARCH@_F_CSRN, @ARCH@_F_CRNX_HI
, @ARCH@_F_CRNX_LO, @ARCH@_F_CRNX, @ARCH@_F_0, @ARCH@_F_1
---------------------------------------------------------------------
As it turns out, gen-ifld-defns does explitictely omit VIRTUAL and
derived ifields when generating @arch@_cgen_ifld_table and
gen-maybe-multi-ifield expects them to be omitted when indexing the
table using ifld-number which generates hard coded indices. However,
Stan is correct that the generated macros 'F' index the table using the
enumerators and so require that all ifields be in the table in the
correct order.
The attached patch changes gen-maybe-multi-ifield to also index the
table using the enumerators (much cleaner) and adds the missing ifields
to the table. Note that some information is not available for the
additional fields (ifld-word-offset, ifld-word-length, ifld-start,
ifld-length) and zeroes are generated in these cases.
ifld-number is no longer used. Should it be removed?
I've also attached a diff of fr30-desc.c so you can see how the
generated code changes.
This has been tested on fr30 and on our internal port.
Seeking approval to commit.
Dave
Index: desc-cpu.scm
===================================================================
RCS file: /cvs/src/src/cgen/desc-cpu.scm,v
retrieving revision 1.13
diff -c -p -r1.13 desc-cpu.scm
*** desc-cpu.scm 2 Dec 2002 21:53:53 -0000 1.13
--- desc-cpu.scm 11 Feb 2003 19:54:01 -0000
*************** static const CGEN_MACH @arch@_cgen_mach_
*** 128,135 ****
(define (gen-ifld-defns)
(logit 2 "Generating ifield table ...\n")
! (let* ((ifld-list (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
! (non-derived-ifields (current-ifld-list))))
(all-attrs (current-ifld-attr-list))
(num-non-bools (attr-count-non-bools all-attrs)))
(string-list
--- 128,134 ----
(define (gen-ifld-defns)
(logit 2 "Generating ifield table ...\n")
! (let* ((ifld-list (current-ifld-list))
(all-attrs (current-ifld-attr-list))
(num-non-bools (attr-count-non-bools all-attrs)))
(string-list
*************** const CGEN_IFLD @arch@_cgen_ifld_table[]
*** 149,160 ****
" { "
(ifld-enum ifld) ", "
"\"" (obj:name ifld) "\", "
! (number->string (ifld-word-offset ifld)) ", "
! (number->string (ifld-word-length ifld)) ", "
! (number->string (ifld-start ifld #f)) ", "
! (number->string (ifld-length ifld)) ", "
(gen-obj-attr-defn 'ifld ifld all-attrs
! num-non-bools gen-A-attr-mask)
" },\n")))
ifld-list)
"\
--- 148,164 ----
" { "
(ifld-enum ifld) ", "
"\"" (obj:name ifld) "\", "
! (if
! (or (has-attr? ifld 'VIRTUAL)
! (derived-ifield? ifld))
! "0, 0, 0, 0,"
! (string-append
! (number->string (ifld-word-offset ifld)) ", "
! (number->string (ifld-word-length ifld)) ", "
! (number->string (ifld-start ifld #f)) ", "
! (number->string (ifld-length ifld)) ", "))
(gen-obj-attr-defn 'ifld ifld all-attrs
! num-non-bools gen-A-attr-mask)
" },\n")))
ifld-list)
"\
*************** const CGEN_HW_ENTRY @arch@_cgen_hw_table
*** 404,410 ****
(set! field-ref (string-append "&" (ifld-enum fld) "_MULTI_IFIELD[0]"))
(set! field-count (number->string (length (elm-get fld 'subfields)))))
; else
! (set! field-ref (string-append "&@arch@_cgen_ifld_table[" (ifld-number fld) "]"))))
(string-append "{ " field-count ", { (const PTR) " field-ref " } }")))
(define (gen-multi-ifield-nodes)
--- 408,414 ----
(set! field-ref (string-append "&" (ifld-enum fld) "_MULTI_IFIELD[0]"))
(set! field-count (number->string (length (elm-get fld 'subfields)))))
; else
! (set! field-ref (string-append "&@arch@_cgen_ifld_table[" (ifld-enum fld) "]"))))
(string-append "{ " field-count ", { (const PTR) " field-ref " } }")))
(define (gen-multi-ifield-nodes)
Index: fr30-desc.c
===================================================================
RCS file: /cvs/src/src/opcodes/fr30-desc.c,v
retrieving revision 1.14
diff -c -p -r1.14 fr30-desc.c
*** fr30-desc.c 2 Dec 2002 21:58:18 -0000 1.14
--- fr30-desc.c 11 Feb 2003 19:59:21 -0000
*************** const CGEN_IFLD fr30_cgen_ifld_table[] =
*** 325,330 ****
--- 325,331 ----
{ FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
{ FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } } },
+ { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
{ FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
*************** const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_M
*** 357,364 ****
const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
{
! { 0, { (const PTR) &fr30_cgen_ifld_table[23] } },
! { 0, { (const PTR) &fr30_cgen_ifld_table[24] } },
{ 0, { (const PTR) 0 } }
};
--- 358,365 ----
const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
{
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
{ 0, { (const PTR) 0 } }
};
*************** const CGEN_OPERAND fr30_cgen_operand_tab
*** 379,417 ****
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
! { 0, { (const PTR) &fr30_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[10] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[9] } },
{ 0, { (1<<MACH_BASE) } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[14] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[16] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[15] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[11] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[12] } },
{ 0, { (1<<MACH_BASE) } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
--- 380,418 ----
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { (1<<MACH_BASE) } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { (1<<MACH_BASE) } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
*************** const CGEN_OPERAND fr30_cgen_operand_tab
*** 431,481 ****
{ 0, { (1<<MACH_BASE) } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[17] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[18] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[21] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[22] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[26] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[27] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[28] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[29] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[30] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[31] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
! { 0, { (const PTR) &fr30_cgen_ifld_table[25] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[20] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
--- 432,482 ----
{ 0, { (1<<MACH_BASE) } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
*************** const CGEN_OPERAND fr30_cgen_operand_tab
*** 483,529 ****
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[33] } },
{ 0, { (1<<MACH_BASE) } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[34] } },
{ 0, { (1<<MACH_BASE) } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[35] } },
{ 0, { (1<<MACH_BASE) } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[32] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
! { 0, { (const PTR) &fr30_cgen_ifld_table[36] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[40] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[39] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[38] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[37] } },
{ 0, { (1<<MACH_BASE) } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[7] } },
{ 0, { (1<<MACH_BASE) } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
--- 484,530 ----
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { (1<<MACH_BASE) } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { (1<<MACH_BASE) } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { (1<<MACH_BASE) } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { (1<<MACH_BASE) } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { (1<<MACH_BASE) } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
! { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,