adjusting cgen

[Johan Rydberg <jrydberg at rtmk dot org>]

Hi!

I'm hacking my way through the CGEN sources to adopt them to generate
targets to a simulator I'm working on.  What I have done is to clone 
the SID-part of CGEN and adjust it to generate code that suits my
simulator.  I better let you know that I know neither Scheme or Lisp.

And I have some questions;

1)  Is it possible to adjust CGEN to recognize on-page branches?
    This could be a huge optimization for me, since this will eliminate
    the full tlb+mmu lookup for (near) branches.  

2)  Is it possible to adjust the -gen-argbuf-elm fn in sid-decode.scm to
    generate bit fields instead of full integers?  Currently it generates
    code similar to this;

    struct { /*  */
      UINT f_rd;
      UINT f_sr;
    } sfmt_mfsr;

    What I would like to do is to reduce the size of the sem_fields union
    to a total of 32-bits (for a 32-bit architecture).  I guess this is
    best done by emitting bit fields, like;

    struct { /*  */
      UINT f_rd : 8;
      UINT f_sr : 8;
    } sfmt_mfsr;
   
    The bit field size should be the length of the ifield, rounded up to
    the next multiple of eight, but only for fields longer than 3 bits.
    (I assume that fields longer than 3 bits is normally either used as 
     indexes in for example the register file, or immediates)

    Is this possible?

I hope some of you understand what I'm trying to communicate (it's
4 am here).

If you're intressted in the simulator, you can find information (ie
the sources) at http://savannah.gnu.org/projects/guss/ .

regards
johan