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[PATCH v4 0/5] x86: operand size handling improvements
- From: Jan Beulich <jbeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Mon, 10 Feb 2020 14:50:56 +0100
- Subject: [PATCH v4 0/5] x86: operand size handling improvements
The main goal continues to be better consistency in the handling of insn
operands, i.e. in particular less unexpected behavior when deducing how
things would behave from observations with one (set of) insn(s) or
operand(s) towards other constructs.
1: x86: also disallow non-byte/-word registers with byte/word suffix
2: x86: move certain MOVSX/MOVZX tests
3: x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX
4: x86: correct VFPCLASSP{S,D} operand size handling
5: x86-64: Intel64 adjustments for insns dealing with far pointers
v4 addresses prior comments, drops 1 patch (leaving aside ones
which simply got committed), and adds 1 new patch. I realize that
patch 5 in particular may need re-basing over "x86: Accept Intel64
only instruction by default", if that goes in earlier.
Jan