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Re: [PATCH] x86: Accept Intel64 only instruction by default
- From: Jan Beulich <jbeulich at suse dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: binutils at sourceware dot org
- Date: Mon, 10 Feb 2020 10:03:34 +0100
- Subject: Re: [PATCH] x86: Accept Intel64 only instruction by default
- References: <20200207203450.3236-1-hjl.tools@gmail.com>
On 07.02.2020 21:34, H.J. Lu wrote:
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -638,10 +638,16 @@ enum
> ATTSyntax,
> /* Intel syntax. */
> IntelSyntax,
> - /* AMD64. */
> - AMD64,
> - /* Intel64. */
> - Intel64,
> + /* ISA64:
> + 0: Common to AMD64 and Intel64.
> + 1: AMD64.
> + 2: Intel64.
> + 3: Only in Intel64.
> + */
> +#define AMD64 1
> +#define INTEL64 2
> +#define INTEL64ONLY 3
> + ISA64,
I think the comment should warn that the order here cannot be
changed without other code adjustments.
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -82,6 +82,10 @@
> #define EVexLIG EVex=EVEXLIG
> #define EVexDYN EVex=EVEXDYN
>
> +#define Amd64 ISA64=AMD64
> +#define Intel64 ISA64=INTEL64
> +#define Intel64Only ISA64=INTEL64ONLY
> +
> // The EVEX purpose of StaticRounding appears only together with SAE. Re-use
> // the bit to mark commutative VEX encodings where swapping the source
> // operands may allow to switch from 3-byte to 2-byte VEX encoding.
Would you mind moving the addition up, at least ahead of all the VEX-/
EVEX-related #define-s?
Thanks, Jan