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[PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling

From: Jan Beulich <JBeulich at suse dot com>
To: "binutils at sourceware dot org" <binutils at sourceware dot org>
Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
Date: Fri, 27 Dec 2019 09:18:41 +0000
Subject: [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling
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References: <a79874b2-6fcd-d65f-1163-2c9d1d8f4826@suse.com>

With AVX512VL disabled (e.g. when writing code for the Knights family
of processors) these insns aren't ambiguous when used with a memory
source, and hence should be accepted without suffix or operand size
specifier. When AVX512VL is enabled, to be consistent with this as
well as other ambiguous operand size handling it seems better to just
warn about the ambiguity in AT&T mode, and still default to 512-bit
operands (on the assumption that the code may have been written without
AVX512VL in mind yet).

gas/
2020-01-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (avx512): New (at file scope), moved from
	(check_VecOperands): ... here.
	(process_suffix): Add [XYZ]MMword operand size handling.
	* testsuite/gas/i386/noavx512-2.s, testsuite/gas/i386/noreg16.s,
	testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s: Add
	VFPCLASS tests.
	* testsuite/gas/i386/noavx512-2.l, testsuite/gas/i386/noreg16.d,
	testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.d,
	testsuite/gas/i386/noreg32.l, testsuite/gas/i386/noreg64.d,
	testsuite/gas/i386/noreg64.l: Adjust expectations.

opcodes/
2020-01-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vfpclasspd, vfpclassps): Add Unspecified.
	* i386-tbl.h: Re-generate.
---
v3: Re-base.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1839,6 +1839,8 @@ cpu_flags_and_not (i386_cpu_flags x, i38
   return x;
 }
 
+static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
+
 #define CPU_FLAGS_ARCH_MATCH		0x1
 #define CPU_FLAGS_64BIT_MATCH		0x2
 
@@ -5352,7 +5354,6 @@ check_VecOperands (const insn_template *
 {
   unsigned int op;
   i386_cpu_flags cpu;
-  static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
 
   /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
      any one operand are implicity requiring AVX512VL support if the actual
@@ -6432,7 +6433,8 @@ process_suffix (void)
       && !i.tm.opcode_modifier.defaultsize
       && !i.tm.opcode_modifier.ignoresize)
     {
-      unsigned int suffixes;
+      unsigned int suffixes, evex = 0;
+      i386_cpu_flags cpu;
 
       suffixes = !i.tm.opcode_modifier.no_bsuf;
       if (!i.tm.opcode_modifier.no_wsuf)
@@ -6446,7 +6448,56 @@ process_suffix (void)
       if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
 	suffixes |= 1 << 5;
 
-      /* Are multiple suffixes allowed?  */
+      /* For [XYZ]MMWORD operands inspect operand sizes.  */
+      cpu = cpu_flags_and (i.tm.cpu_flags, avx512);
+      if (!cpu_flags_all_zero (&cpu)
+	  && !i.broadcast)
+	{
+	  unsigned int op;
+
+	  for (op = 0; op < i.tm.operands; ++op)
+	    {
+	      if (!cpu_arch_flags.bitfield.cpuavx512vl)
+		{
+		  if (i.tm.operand_types[op].bitfield.ymmword)
+		    i.tm.operand_types[op].bitfield.xmmword = 0;
+		  if (i.tm.operand_types[op].bitfield.zmmword)
+		    i.tm.operand_types[op].bitfield.ymmword = 0;
+		  if (!i.tm.opcode_modifier.evex
+		      || i.tm.opcode_modifier.evex == EVEXDYN)
+		    i.tm.opcode_modifier.evex = EVEX512;
+		}
+
+	      if (i.tm.operand_types[op].bitfield.xmmword
+		  + i.tm.operand_types[op].bitfield.ymmword
+		  + i.tm.operand_types[op].bitfield.zmmword < 2)
+		continue;
+
+	      /* Any properly sized operand disambiguates the insn.  */
+	      if (i.types[op].bitfield.xmmword
+		  || i.types[op].bitfield.ymmword
+		  || i.types[op].bitfield.zmmword)
+		{
+		  suffixes &= ~(7 << 6);
+		  evex = 0;
+		  break;
+		}
+
+	      if ((i.flags[op] & Operand_Mem)
+		  && i.tm.operand_types[op].bitfield.unspecified)
+		{
+		  if (i.tm.operand_types[op].bitfield.xmmword)
+		    suffixes |= 1 << 6;
+		  if (i.tm.operand_types[op].bitfield.ymmword)
+		    suffixes |= 1 << 7;
+		  if (i.tm.operand_types[op].bitfield.zmmword)
+		    suffixes |= 1 << 8;
+		  evex = EVEX512;
+		}
+	    }
+	}
+
+      /* Are multiple suffixes / operand sizes allowed?  */
       if (suffixes & (suffixes - 1))
 	{
 	  if (intel_syntax)
@@ -6469,6 +6520,8 @@ process_suffix (void)
 	    i.suffix = SHORT_MNEM_SUFFIX;
 	  else if ((i.tm.base_opcode | 8) == 0xfbe || i.tm.base_opcode == 0x63)
 	    /* handled below */;
+	  else if (evex)
+	    i.tm.opcode_modifier.evex = evex;
 	  else if (flag_code == CODE_16BIT)
 	    i.suffix = WORD_MNEM_SUFFIX;
 	  else if (!i.tm.opcode_modifier.no_lsuf)
--- a/gas/testsuite/gas/i386/noavx512-2.l
+++ b/gas/testsuite/gas/i386/noavx512-2.l
@@ -101,5 +101,10 @@ GAS LISTING .*
 [ 	]*50[ 	]+F5
 [ 	]*51[ 	]+\?\?\?\? 660F58F4 		addpd %xmm4, %xmm6
 [ 	]*52[ 	]+
-[ 	]*53[ 	]+\?\?\?\? 0F1F00   		\.p2align 4
+[ 	]*[1-9][0-9]*[ 	]+\?\?\?\? 62F3FD48 		vfpclasspd \$0, \(%eax\), %k0
+[ 	]*[1-9][0-9]*[ 	]+660000
+[ 	]*[1-9][0-9]*[ 	]+\?\?\?\? 62F37D48 		vfpclassps \$0, \(%eax\), %k0
+[ 	]*[1-9][0-9]*[ 	]+660000
+[ 	]*[1-9][0-9]*[ 	]+
+[ 	]*[1-9][0-9]*[ 	].*\.p2align 4
 #pass
--- a/gas/testsuite/gas/i386/noavx512-2.s
+++ b/gas/testsuite/gas/i386/noavx512-2.s
@@ -50,4 +50,7 @@
 	pabsb %xmm5, %xmm6
 	addpd %xmm4, %xmm6
 
+	vfpclasspd $0, (%eax), %k0
+	vfpclassps $0, (%eax), %k0
+
 	.p2align 4
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -145,6 +145,8 @@ Disassembly of section .text:
  *[a-f0-9]+:	62 f1 7e 08 2a 07    	vcvtsi2ssl \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7f 08 7b 07    	vcvtusi2sdl \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 07    	vcvtusi2ssl \(%bx\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f3 fd 48 66 07 00 	vfpclasspdz \$0x0,\(%bx\),%k0
+ *[a-f0-9]+:	62 f3 7d 48 66 07 00 	vfpclasspsz \$0x0,\(%bx\),%k0
  *[a-f0-9]+:	83 37 01             	xorw   \$0x1,\(%bx\)
  *[a-f0-9]+:	81 37 89 00          	xorw   \$0x89,\(%bx\)
  *[a-f0-9]+:	81 37 34 12          	xorw   \$0x1234,\(%bx\)
--- a/gas/testsuite/gas/i386/noreg16.l
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -113,6 +113,8 @@
 .*:[1-9][0-9]*: Warning: .* `sub'
 .*:[1-9][0-9]*: Warning: .* `test'
 .*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vfpclasspd'
+.*:[1-9][0-9]*: Warning: .* `vfpclassps'
 .*:[1-9][0-9]*: Warning: .* `xor'
 .*:[1-9][0-9]*: Warning: .* `xor'
 .*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -139,6 +139,8 @@ noreg:
 	{evex} vcvtsi2ss (%bx), %xmm0, %xmm0
 	vcvtusi2sd (%bx), %xmm0, %xmm0
 	vcvtusi2ss (%bx), %xmm0, %xmm0
+	vfpclasspd $0, (%bx), %k0
+	vfpclassps $0, (%bx), %k0
 	xor	$1, (%bx)
 	xor	$0x89, (%bx)
 	xor	$0x1234, (%bx)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -154,6 +154,8 @@ Disassembly of section .text:
  *[a-f0-9]+:	62 f1 7e 08 2a 00    	vcvtsi2ssl \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7f 08 7b 00    	vcvtusi2sdl \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 00    	vcvtusi2ssl \(%eax\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f3 fd 48 66 00 00 	vfpclasspdz \$0x0,\(%eax\),%k0
+ *[a-f0-9]+:	62 f3 7d 48 66 00 00 	vfpclasspsz \$0x0,\(%eax\),%k0
  *[a-f0-9]+:	83 30 01             	xorl   \$0x1,\(%eax\)
  *[a-f0-9]+:	81 30 89 00 00 00    	xorl   \$0x89,\(%eax\)
  *[a-f0-9]+:	81 30 34 12 00 00    	xorl   \$0x1234,\(%eax\)
--- a/gas/testsuite/gas/i386/noreg32.l
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -122,6 +122,8 @@
 .*:[1-9][0-9]*: Warning: .* `test'
 .*:[1-9][0-9]*: Warning: .* `test'
 .*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vfpclasspd'
+.*:[1-9][0-9]*: Warning: .* `vfpclassps'
 .*:[1-9][0-9]*: Warning: .* `xor'
 .*:[1-9][0-9]*: Warning: .* `xor'
 .*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -147,6 +147,8 @@ noreg:
 	{evex} vcvtsi2ss (%eax), %xmm0, %xmm0
 	vcvtusi2sd (%eax), %xmm0, %xmm0
 	vcvtusi2ss (%eax), %xmm0, %xmm0
+	vfpclasspd $0, (%eax), %k0
+	vfpclassps $0, (%eax), %k0
 	xor	$1, (%eax)
 	xor	$0x89, (%eax)
 	xor	$0x1234, (%eax)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -158,6 +158,8 @@ Disassembly of section .text:
  *[a-f0-9]+:	62 61 7e 08 2a 38    	vcvtsi2ssl \(%rax\),%xmm0,%xmm31
  *[a-f0-9]+:	62 f1 7f 08 7b 00    	vcvtusi2sdl \(%rax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 00    	vcvtusi2ssl \(%rax\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f3 fd 48 66 00 00 	vfpclasspdz \$0x0,\(%rax\),%k0
+ *[a-f0-9]+:	62 f3 7d 48 66 00 00 	vfpclasspsz \$0x0,\(%rax\),%k0
  *[a-f0-9]+:	83 30 01             	xorl   \$0x1,\(%rax\)
  *[a-f0-9]+:	81 30 89 00 00 00    	xorl   \$0x89,\(%rax\)
  *[a-f0-9]+:	81 30 34 12 00 00    	xorl   \$0x1234,\(%rax\)
--- a/gas/testsuite/gas/i386/noreg64.l
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -135,6 +135,8 @@
 .*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
 .*:[1-9][0-9]*: Warning: .* `vcvtusi2sd'
 .*:[1-9][0-9]*: Warning: .* `vcvtusi2ss'
+.*:[1-9][0-9]*: Warning: .* `vfpclasspd'
+.*:[1-9][0-9]*: Warning: .* `vfpclassps'
 .*:[1-9][0-9]*: Warning: .* `xor'
 .*:[1-9][0-9]*: Warning: .* `xor'
 .*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -151,6 +151,8 @@ noreg:
 	vcvtsi2ss (%rax), %xmm0, %xmm31
 	vcvtusi2sd (%rax), %xmm0, %xmm0
 	vcvtusi2ss (%rax), %xmm0, %xmm0
+	vfpclasspd $0, (%rax), %k0
+	vfpclassps $0, (%rax), %k0
 	xor	$1, (%rax)
 	xor	$0x89, (%rax)
 	xor	$0x1234, (%rax)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4500,12 +4500,12 @@ vextracti64x2, 3, 0x6639, None, 1, CpuAV
 vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
 vinserti64x2, 4, 0x6638, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
 
-vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask }
+vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegMask }
 vfpclasspdz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|Unspecified|BaseIndex, RegMask }
 vfpclasspdx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
 vfpclasspdy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|Unspecified|BaseIndex, RegMask }
 
-vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask }
+vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegMask }
 vfpclasspsz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Dword|Unspecified|BaseIndex, RegMask }
 vfpclasspsx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
 vfpclasspsy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|Unspecified|BaseIndex, RegMask }

References:
- [PATCH v3 00/10] x86: operand size handling improvements
  - From: Jan Beulich

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